Merge pull request #104 from the-snowwhite/work

Work

Author: ArcEye

HW/QuartusProjects/.gitignore

@@ -56,7 +56,7 @@
 *.pin
 *.hex
 *.ddb
-#*.stp
+*.stp
 *.rar
 *.dpf
 *.qdf
@@ -82,3 +82,6 @@ software/
 stamp/
 # ignore qsys generated folder
 .qsys_edit/
+# ignore build generated files
+*.mif
+*.qip

HW/QuartusProjects/Common/capsense.sv

@@ -8,13 +8,14 @@
 
 module capsense
 (
-	input	clk, reset,
-	input [num-1:0] sense,
-	input [3:0] hysteresis [num-1:0],
-	output [11:0] calibval_0,
-	output [11:0] counts_0,
-	output reg charge,
-	output reg [num-1:0] touched
+    input   clk,
+    input   reset,
+    input [num-1:0] sense,
+    input [3:0] hysteresis [num-1:0],
+//    output [11:0] calibval_0,
+//    output [11:0] counts_0,
+    output reg charge,
+    output reg [num-1:0] touched
 );
 
 	parameter num = 4;
@@ -51,8 +52,8 @@ module capsense
 
 	wire [11:0] actual_count = period_count - counter;
 
-	assign calibval_0 = calibval[0];
-	assign counts_0 = counts[0];
+//	assign calibval_0 = calibval[0];
+//	assign counts_0 = counts[0];
 
 	genvar ii;
 	integer i1, i2, i3, i4, i5, i6, l1, l2, l3;

HW/QuartusProjects/Common/gpio_adr_decoder_reg.sv

@@ -64,8 +64,8 @@ module gpio_adr_decoder_reg(
     output                              ADC_SDI_o,
     input                               ADC_SDO_i,
 //	Touch sensor:
-    output  [11:0]                      calibval_0,
-    output  [13:0]                      counts_0,
+//    output  [11:0]                      calibval_0,
+//    output  [13:0]                      counts_0,
     output  [NumSense-1:0]              touched,
     input   [1:0]                       buttons
 );
@@ -146,13 +146,20 @@ parameter   TotalNumregs    = Mux_regPrIOReg * NumIOAddrReg * NumPinsPrIOAddr;
     wire [31:0]adc_data_out;
 
 // Touch sensor:
+    reg [BusWidth-1:0]  hysteresis_reg;
+    reg [1:0]sr_delay;
+    reg reset_sr;
+    reg [2:0]sr_init_delay;
+    reg reset_init_sr;
     wire [NumSense-1:0] sense;
     wire                charge;
-    reg [BusWidth-1:0]  hysteresis_reg;
     wire [3:0]          hysteresis[NumSense-1:0];
-
-    wire sense_reset    = ~reset_reg_N | ~buttons[1];
-
+    
+    wire sr_delay_act; 
+    wire sr_init_delay_act; 
+   wire sense_reset;
+//	wire sense_reset = ~reset_reg_N;
+    
     genvar sh;
     generate
         for(sh=0;sh<NumSense;sh=sh+1) begin : sense_hystloop
@@ -256,15 +263,35 @@ generate if (Capsense >= 1) begin
     // Writes:
     always @( posedge reset_in or posedge write_address) begin
         if (reset_in) begin
-            hysteresis_reg <= 32'h11111111;
+            hysteresis_reg <= 32'h22222222;
+            reset_sr <= 1'b0;
         end
         else if ( write_address ) begin
-            if (busaddress_r == 10'h0304) begin hysteresis_reg  <= busdata_in_r; end
-        end
+            if (busaddress_r == 10'h0304) begin
+                hysteresis_reg  <= busdata_in_r; 
+                reset_sr <= 1'b1;
+            end 
+            else begin
+                hysteresis_reg  <= hysteresis_reg; 
+                reset_sr <= 1'b0;
+            end
+        end	
     end
 end
 endgenerate
 
+    always @(posedge reg_clk) begin
+        sr_delay[0] <= reset_sr;
+        sr_delay[1] <= sr_delay[0];
+        sr_init_delay[0] <= reset_init_sr;
+        sr_init_delay[1] <= sr_init_delay[0];
+        sr_init_delay[2] <= sr_init_delay[1];
+    end
+    
+    assign sr_delay_act = (sr_delay[1] == 1'b1 && sr_delay[0] == 1'b0)  ? 1'b1 : 1'b0;
+    assign sr_init_delay_act = (sr_init_delay[2] == 1'b0 && sr_init_delay[0] == 1'b1) ? 1'b1 : 1'b0;
+    assign sense_reset    = ~reset_reg_N | ~buttons[1] | sr_delay_act | sr_init_delay_act;
+    
     genvar il;
     generate
         for(il=0;il<NumIOAddrReg;il=il+1) begin : reg_initloop
@@ -356,11 +383,12 @@ endgenerate
     always @(posedge reset_in or posedge read_address)begin
         if (reset_in)begin
             busdata_to_cpu <= 32'b0;
+            reset_init_sr <= 1'b0;
         end
         else if (read_address) begin
             if (Capsense >= 1) begin
                 if (adc_address_valid) begin busdata_to_cpu <= adc_data_out;	end
-                else if (busaddress_r == 'h0300) begin busdata_to_cpu <= touched;	end
+                else if (busaddress_r == 'h0300) begin busdata_to_cpu <= touched; reset_init_sr <= 1'b1;	end
                 else if (busaddress_r == 'h0304) begin busdata_to_cpu <= hysteresis_reg;	end
                 else if(busaddress_r == 'h1000) begin busdata_to_cpu <= {8'b0,gpio_input_data[0][23:0]}; end
                 else if(busaddress_r == 'h1004) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][11:0],gpio_input_data[0][35:24]}; end
@@ -422,8 +450,8 @@ generate if (Capsense >=1) begin
             .reset(sense_reset) ,	// input  reset_sig
             .sense(sense) ,	// input [num-1:0] sense_sig
             .hysteresis(hysteresis),
-            .calibval_0(calibval_0),
-            .counts_0(counts_0),
+//            .calibval_0(calibval_0),
+//            .counts_0(counts_0),
             .charge(charge) ,	// output  charge_sig
             .touched(touched) 	// output [num-1:0] touched_sig
         );

HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.qsf

@@ -649,7 +649,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
 set_global_assignment -name SDC_FILE DE0_Nano_SoC_Cramps.sdc
 set_global_assignment -name VHDL_FILE ../Common/firmware_id.vhd
 set_global_assignment -name MIF_FILE firmware_id.mif
-set_global_assignment -name QIP_FILE hm3_DE0_Nano_SoC.qip
+set_global_assignment -name QIP_FILE hm3_DE0_Nano_SoC_Cramps.qip
 set_global_assignment -name QIP_FILE ../../hm2/hm3_socfpga.qip
 set_global_assignment -name QIP_FILE hm3_pin_config.qip
 set_global_assignment -name SYSTEMVERILOG_FILE ../Common/capsense.sv
@@ -663,4 +663,4 @@ set_global_assignment -name SYSTEMVERILOG_FILE ../Common/adc_ltc2308_fifo.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../Common/bidir_io.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../Common/gpio_adr_decoder_reg.sv
 set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.sv

@@ -145,7 +145,7 @@ parameter NumIOAddrReg = 6;
 
 
 // connection of internal logics
-    assign LED[5:1] = fpga_led_internal;
+//    assign LED[5:1] = fpga_led_internal;
     assign fpga_clk_50 = FPGA_CLK1_50;
 //    assign stm_hw_events    = {{15{1'b0}}, SW, fpga_led_internal, fpga_debounced_buttons};
 // hm2
@@ -176,6 +176,12 @@ parameter NumIOAddrReg = 6;
     wire int_sig;
     assign ARDUINO_IO[15] = int_sig;
 
+// Capsense:
+	wire [NumSense-1:0] 	touched;
+
+// connection of internal logics
+    assign LED[4:1] = touched;
+
 //=======================================================
 //  Structural coding
 //=======================================================
@@ -342,6 +348,8 @@ gpio_adr_decoder_reg gpio_adr_decoder_reg_inst
     .ADC_SCK_o(ADC_SCK),	// output  ADC_SCK_o_sig
     .ADC_SDI_o(ADC_SDI),	// output  ADC_SDI_o_sig
     .ADC_SDO_i(ADC_SDO),	// input  ADC_SDO_i_sig
+// CAP_Sensors
+	.touched(touched),
     .buttons(fpga_debounced_buttons)
 );
 
@@ -351,8 +359,9 @@ defparam gpio_adr_decoder_reg_inst.GPIOWidth = GPIOWidth;
 defparam gpio_adr_decoder_reg_inst.MuxGPIOIOWidth = MuxGPIOIOWidth;
 defparam gpio_adr_decoder_reg_inst.NumIOAddrReg = NumIOAddrReg;
 defparam gpio_adr_decoder_reg_inst.NumGPIO = NumGPIO;
+defparam gpio_adr_decoder_reg_inst.ADC = ADC;
 defparam gpio_adr_decoder_reg_inst.Capsense = Capsense;
-defparam gpio_adr_decoder_reg_inst.NumSense = 4;
+defparam gpio_adr_decoder_reg_inst.NumSense = NumSense;
 
 HostMot3_cfg HostMot3_inst
 (

HW/QuartusProjects/DE0_Nano_SoC_Cramps/build.sh

@@ -31,7 +31,7 @@ OUTPUTDIR=output_files
 set -e
 
 # Path to the configuration files
-CONFIG_DIR="../../hm2/config/${BOARDNAME}"
+CONFIG_DIR="../../hm2/config/DExx_Nano_xxx_Cramps"
 
 
 # Routine to build a specific configuration
@@ -43,7 +43,7 @@ build_config() {
     # which means in rare instances it could match actual VHDL code.  Here we use
     # the % character to support a batch-style variable scheme
     sed "s/%CONFIG%/${1}/g" <${CONFIG_DIR}/hm3_pin_config.in > hm3_pin_config.qip
-    sed "s/%CONFIG%/${1}/g" <${CONFIG_DIR}/hm3_DE0_Nano_SoC.in > hm3_DE0_Nano_SoC.qip
+    sed "s/%CONFIG%/${1}/g" <${CONFIG_DIR}/hm3_DExx_Nano_xxx_Cramps.in > hm3_${BOARDNAME}.qip
 
     # Actually build the FPGA bit file
     make rbf

HW/QuartusProjects/DE0_Nano_SoC_Cramps/firmware_id.mif

@@ -144,9 +144,12 @@ parameter NumIOAddrReg = 6;
 
     wire        lcd_clk;
 
+    wire [NumSense-1:0] touched;
 // connection of internal logics
-    assign LED[5:1] = fpga_led_internal;
-    assign fpga_clk_50 = FPGA_CLK1_50;
+//	assign LED[5:1] = fpga_led_internal | {7'b0000000, led_level};
+    assign LED[4:1] = touched;
+    
+    assign fpga_clk_50=FPGA_CLK1_50;
 //    assign stm_hw_events    = {{15{1'b0}}, SW, fpga_led_internal, fpga_debounced_buttons};
 // hm2
     wire [AddrWidth-1:2]    hm_address;
@@ -342,6 +345,7 @@ gpio_adr_decoder_reg gpio_adr_decoder_reg_inst
     .ADC_SCK_o(ADC_SCK),	// output  ADC_SCK_o_sig
     .ADC_SDI_o(ADC_SDI),	// output  ADC_SDI_o_sig
     .ADC_SDO_i(ADC_SDO),	// input  ADC_SDO_i_sig
+    .touched(touched),	// input  ADC_SDO_i_sig
     .buttons(fpga_debounced_buttons)
 );
 
@@ -351,8 +355,9 @@ defparam gpio_adr_decoder_reg_inst.GPIOWidth = GPIOWidth;
 defparam gpio_adr_decoder_reg_inst.MuxGPIOIOWidth = MuxGPIOIOWidth;
 defparam gpio_adr_decoder_reg_inst.NumIOAddrReg = NumIOAddrReg;
 defparam gpio_adr_decoder_reg_inst.NumGPIO = NumGPIO;
+defparam gpio_adr_decoder_reg_inst.ADC = ADC;
 defparam gpio_adr_decoder_reg_inst.Capsense = Capsense;
-defparam gpio_adr_decoder_reg_inst.NumSense = 4;
+defparam gpio_adr_decoder_reg_inst.NumSense = NumSense;
 
 HostMot3_cfg HostMot3_inst
 (