Skip to content

Commit 8dcf674

Browse files
the-snowwhitethe-snowwhite
committed
DE10_Nano_Soc_Cramps: FB Fix: remove jtag from framebuffer bus in qsys
Signed-off-by: Michael Brown <producer@holotronic.dk>
1 parent 0746170 commit 8dcf674

File tree

2 files changed

+23
-106
lines changed

2 files changed

+23
-106
lines changed

‎HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -172,7 +172,7 @@ soc_system u0 (
172172
//Clock&Reset
173173
.clk_clk (FPGA_CLK1_50 ), // clk.clk
174174
.reset_reset_n (hps_fpga_reset_n ), // reset.reset_n
175-
.alt_vip_itc_0_clocked_video_vid_clk (HDMI_TX_CLK ), // alt_vip_itc_0_clocked_video.vid_clk
175+
.alt_vip_itc_0_clocked_video_vid_clk (clk_75 ), // alt_vip_itc_0_clocked_video.vid_clk
176176
.alt_vip_itc_0_clocked_video_vid_data (HDMI_TX_D ), // .vid_data
177177
.alt_vip_itc_0_clocked_video_underflow ( ), // .underflow
178178
.alt_vip_itc_0_clocked_video_vid_datavalid (HDMI_TX_DE), // .vid_datavalid

‎HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system.qsys‎

Lines changed: 22 additions & 105 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
{
1414
datum _sortIndex
1515
{
16-
value = "11";
16+
value = "10";
1717
type = "int";
1818
}
1919
}
@@ -34,15 +34,15 @@
3434
{
3535
datum _sortIndex
3636
{
37-
value = "13";
37+
value = "12";
3838
type = "int";
3939
}
4040
}
4141
element alt_vip_vfr_hdmi
4242
{
4343
datum _sortIndex
4444
{
45-
value = "12";
45+
value = "11";
4646
type = "int";
4747
}
4848
}
@@ -63,7 +63,7 @@
6363
{
6464
datum _sortIndex
6565
{
66-
value = "8";
66+
value = "7";
6767
type = "int";
6868
}
6969
datum sopceditor_expanded
@@ -102,7 +102,7 @@
102102
{
103103
datum _sortIndex
104104
{
105-
value = "9";
105+
value = "8";
106106
type = "int";
107107
}
108108
datum sopceditor_expanded
@@ -132,14 +132,6 @@
132132
type = "String";
133133
}
134134
}
135-
element f2sdram_only_master
136-
{
137-
datum _sortIndex
138-
{
139-
value = "6";
140-
type = "int";
141-
}
142-
}
143135
element fpga_only_master
144136
{
145137
datum _sortIndex
@@ -157,7 +149,7 @@
157149
{
158150
datum _sortIndex
159151
{
160-
value = "16";
152+
value = "15";
161153
type = "int";
162154
}
163155
}
@@ -215,7 +207,7 @@
215207
{
216208
datum _sortIndex
217209
{
218-
value = "15";
210+
value = "14";
219211
type = "int";
220212
}
221213
}
@@ -257,7 +249,7 @@
257249
{
258250
datum _sortIndex
259251
{
260-
value = "10";
252+
value = "9";
261253
type = "int";
262254
}
263255
datum sopceditor_expanded
@@ -283,7 +275,7 @@
283275
{
284276
datum _sortIndex
285277
{
286-
value = "7";
278+
value = "6";
287279
type = "int";
288280
}
289281
}
@@ -299,7 +291,7 @@
299291
{
300292
datum _sortIndex
301293
{
302-
value = "14";
294+
value = "13";
303295
type = "int";
304296
}
305297
}
@@ -335,6 +327,14 @@
335327
type = "String";
336328
}
337329
}
330+
element soc_system
331+
{
332+
datum _originalDeviceFamily
333+
{
334+
value = "Cyclone V";
335+
type = "String";
336+
}
337+
}
338338
element sysid_qsys
339339
{
340340
datum _sortIndex
@@ -486,7 +486,7 @@
486486
<parameter name="AUTO_CLOCK_MASTER_CLOCK_RATE" value="150000000" />
487487
<parameter name="AUTO_CLOCK_RESET_CLOCK_RATE" value="150000000" />
488488
<parameter name="BITS_PER_PIXEL_PER_COLOR_PLANE" value="8" />
489-
<parameter name="CLOCKS_ARE_SEPARATE" value="1" />
489+
<parameter name="CLOCKS_ARE_SEPARATE" value="0" />
490490
<parameter name="FAMILY" value="Cyclone V" />
491491
<parameter name="MAX_IMAGE_HEIGHT" value="768" />
492492
<parameter name="MAX_IMAGE_WIDTH" value="1024" />
@@ -530,20 +530,6 @@
530530
<parameter name="simDrivenValue" value="0" />
531531
<parameter name="width" value="4" />
532532
</module>
533-
<module
534-
name="f2sdram_only_master"
535-
kind="altera_jtag_avalon_master"
536-
version="15.1"
537-
enabled="1">
538-
<parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
539-
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
540-
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
541-
<parameter name="COMPONENT_CLOCK" value="0" />
542-
<parameter name="FAST_VER" value="0" />
543-
<parameter name="FIFO_DEPTHS" value="2" />
544-
<parameter name="PLI_PORT" value="50000" />
545-
<parameter name="USE_PLI" value="0" />
546-
</module>
547533
<module
548534
name="fpga_only_master"
549535
kind="altera_jtag_avalon_master"
@@ -1526,15 +1512,6 @@
15261512
<parameter name="baseAddress" value="0x0000" />
15271513
<parameter name="defaultConnection" value="false" />
15281514
</connection>
1529-
<connection
1530-
kind="avalon"
1531-
version="15.1"
1532-
start="f2sdram_only_master.master"
1533-
end="hps_0.f2h_sdram0_data">
1534-
<parameter name="arbitrationPriority" value="1" />
1535-
<parameter name="baseAddress" value="0x0000" />
1536-
<parameter name="defaultConnection" value="false" />
1537-
</connection>
15381515
<connection
15391516
kind="avalon"
15401517
version="15.1"
@@ -1615,11 +1592,6 @@
16151592
start="clk_0.clk"
16161593
end="hps_0.h2f_lw_axi_clock" />
16171594
<connection kind="clock" version="15.1" start="clk_0.clk" end="pll_stream.refclk" />
1618-
<connection
1619-
kind="clock"
1620-
version="15.1"
1621-
start="pll_stream.outclk0"
1622-
end="f2sdram_only_master.clk" />
16231595
<connection
16241596
kind="clock"
16251597
version="15.1"
@@ -1715,11 +1687,6 @@
17151687
version="15.1"
17161688
start="clk_0.clk_reset"
17171689
end="fpga_only_master.clk_reset" />
1718-
<connection
1719-
kind="reset"
1720-
version="15.1"
1721-
start="clk_0.clk_reset"
1722-
end="f2sdram_only_master.clk_reset" />
17231690
<connection
17241691
kind="reset"
17251692
version="15.1"
@@ -1779,58 +1746,8 @@
17791746
<connection
17801747
kind="reset"
17811748
version="15.1"
1782-
start="f2sdram_only_master.master_reset"
1783-
end="f2sdram_only_master.clk_reset" />
1784-
<connection
1785-
kind="reset"
1786-
version="15.1"
1787-
start="f2sdram_only_master.master_reset"
1788-
end="fpga_only_master.clk_reset" />
1789-
<connection
1790-
kind="reset"
1791-
version="15.1"
1792-
start="f2sdram_only_master.master_reset"
1793-
end="hps_only_master.clk_reset" />
1794-
<connection
1795-
kind="reset"
1796-
version="15.1"
1797-
start="f2sdram_only_master.master_reset"
1798-
end="alt_vip_itc_0.is_clk_rst_reset" />
1799-
<connection
1800-
kind="reset"
1801-
version="15.1"
1802-
start="f2sdram_only_master.master_reset"
1803-
end="button_pio.reset" />
1804-
<connection
1805-
kind="reset"
1806-
version="15.1"
1807-
start="f2sdram_only_master.master_reset"
1808-
end="dipsw_pio.reset" />
1809-
<connection
1810-
kind="reset"
1811-
version="15.1"
1812-
start="f2sdram_only_master.master_reset"
1813-
end="jtag_uart.reset" />
1814-
<connection
1815-
kind="reset"
1816-
version="15.1"
1817-
start="f2sdram_only_master.master_reset"
1818-
end="led_pio.reset" />
1819-
<connection
1820-
kind="reset"
1821-
version="15.1"
1822-
start="f2sdram_only_master.master_reset"
1823-
end="sysid_qsys.reset" />
1824-
<connection
1825-
kind="reset"
1826-
version="15.1"
1827-
start="f2sdram_only_master.master_reset"
1828-
end="pll_stream.reset" />
1829-
<connection
1830-
kind="reset"
1831-
version="15.1"
1832-
start="f2sdram_only_master.master_reset"
1833-
end="hm2reg_io_0.reset" />
1749+
start="clk_0.clk_reset"
1750+
end="intr_capturer_0.reset_sink" />
18341751
<connection
18351752
kind="reset"
18361753
version="15.1"
@@ -1839,7 +1756,7 @@
18391756
<connection
18401757
kind="reset"
18411758
version="15.1"
1842-
start="f2sdram_only_master.master_reset"
1759+
start="fpga_only_master.master_reset"
18431760
end="intr_capturer_0.reset_sink" />
18441761
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
18451762
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />

0 commit comments

Comments
 (0)