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the-snowwhitethe-snowwhite
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Add Myirtech MYD-CZU3EG/4EV aka UltraMyir Development Board
Signed-off-by: Holotronic <producer@holotronic.dk>
1 parent cbd1057 commit 7a0edc4

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‎HW/VivadoProjects/make_bitfile.sh‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,8 +83,8 @@ cd ../VivadoProjects
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# Run the tcl script to build the project and generate the bitfile
8484
/tools/Xilinx/Vivado/2019.1/bin/vivado -mode batch -source "$PRJ_FILE"
8585

86-
# bootgen: skip ultre96 projects
87-
if test "${1#*"ultra96"}" = "$1" && test "${1#*"fz3"}" = "$1"; then
86+
# bootgen: skip mpsoc projects
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if test "${1#*"ultra96"}" = "$1" && test "${1#*"fz3"}" = "$1" && test "${1#*"ultramyir"}" = "$1"; then
8888

8989
# Update the bif file for bootgen
9090
# component file1 needs the pin file path

‎HW/VivadoProjects/make_mpsoc_boot.sh‎

Lines changed: 20 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -16,19 +16,28 @@ fi
1616

1717
CUR_DIR=`realpath .`
1818

19+
case $1 in
1920

20-
if [[ $1 == *"ultra96"* ]]; then
21-
cd /work/avnet/ultra96
21+
*"ultra96"*)
22+
cd /work/HW/VivadoProjects/avnet/ultra96
2223
BOARD_PART="xczu3eg"
23-
else
24-
if [[ $1 == *"fz3"* ]]; then
25-
cd /work//myirtech/fz3
26-
BOARD_PART="xczu3eg"
27-
else
28-
echo "cant't find board project folder"
29-
exit 1
30-
fi
31-
fi
24+
;;
25+
26+
*"fz3"*)
27+
cd /work/HW/VivadoProjects/myirtech/fz3
28+
BOARD_PART="xczu3eg"
29+
;;
30+
31+
*"ultramyir"*)
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cd /work/HW/VivadoProjects/myirtech/ultramyir
33+
BOARD_PART="xczu3eg"
34+
;;
35+
36+
*)
37+
echo "cant't find board project folder"
38+
exit 1
39+
;;
40+
esac
3241

3342
petalinux-create -t project -s "$1"-mk-2019.1.bsp
3443
cd "$1"-mk-2019.1

‎HW/VivadoProjects/myirtech/ultramyir/const/PIN_ULTRAMYIR_36.vhd‎

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1+
library IEEE;
2+
use IEEE.std_logic_1164.all; -- defines std_logic types
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use IEEE.STD_LOGIC_ARITH.ALL;
4+
use IEEE.STD_LOGIC_UNSIGNED.ALL;
5+
6+
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
8+
--
9+
-- Ported to MYIR ZTURN IO Carrier board:
10+
-- Copyright (C) 2016, Devin Hughes, JD Squared
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-- http://www.jd2.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
15+
-- licensing terms:
16+
--
17+
-- * GNU General Public License (GPL), version 2.0 or later
18+
-- * 3-clause BSD License
19+
--
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--
21+
-- The GNU GPL License:
22+
--
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-- This program is free software; you can redistribute it and/or modify
24+
-- it under the terms of the GNU General Public License as published by
25+
-- the Free Software Foundation; either version 2 of the License, or
26+
-- (at your option) any later version.
27+
--
28+
-- This program is distributed in the hope that it will be useful,
29+
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
30+
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31+
-- GNU General Public License for more details.
32+
--
33+
-- You should have received a copy of the GNU General Public License
34+
-- along with this program; if not, write to the Free Software
35+
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36+
--
37+
--
38+
-- The 3-clause BSD License:
39+
--
40+
-- Redistribution and use in source and binary forms, with or without
41+
-- modification, are permitted provided that the following conditions
42+
-- are met:
43+
--
44+
-- * Redistributions of source code must retain the above copyright
45+
-- notice, this list of conditions and the following disclaimer.
46+
--
47+
-- * Redistributions in binary form must reproduce the above
48+
-- copyright notice, this list of conditions and the following
49+
-- disclaimer in the documentation and/or other materials
50+
-- provided with the distribution.
51+
--
52+
-- * Neither the name of Mesa Electronics nor the names of its
53+
-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
55+
-- permission.
56+
--
57+
--
58+
-- Disclaimer:
59+
--
60+
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
61+
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
63+
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
66+
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
67+
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
68+
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69+
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
70+
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
71+
-- POSSIBILITY OF SUCH DAMAGE.
72+
--
73+
74+
use work.IDROMConst.all;
75+
76+
package PIN_ULTRAMYIR_36 is
77+
constant ModuleID : ModuleIDType :=(
78+
(HM2DPLLTag, x"00", ClockLowTag, x"04", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
79+
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
80+
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
81+
(StepGenTag, x"02", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
82+
(FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask),
83+
(PWMTag, x"00", ClockHighTag, x"03", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
84+
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
85+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
86+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
87+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
88+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
89+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
90+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
91+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
92+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
93+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
94+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
95+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
96+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
97+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
98+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
99+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
100+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
101+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
102+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
103+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
104+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
105+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
106+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
107+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
108+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
109+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
110+
);
111+
112+
113+
constant PinDesc : PinDescType :=(
114+
-- Base func sec unit sec func sec pin -- hostmot2 Header Pin Func HD = 3V3, SD = 1V8
115+
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 HD_GPIO0_0 Pmod0_0 A Dir
116+
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 HD_GPIO0_1 Pmod0_1 A Step
117+
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 HD_GPIO0_2 Pmod0_2 B Dir
118+
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 HD_GPIO0_3 Pmod0_3 B Step
119+
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 HD_GPIO0_4 Pmod0_4 C Dir
120+
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 HD_GPIO0_5 Pmod0_5 C Step
121+
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06 HD_GPIO0_6 Pmod0_6 D Dir
122+
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07 HD_GPIO0_7 Pmod0_7 D Step
123+
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 08 HD_GPIO0_8 Pmod1_0 E Dir
124+
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 09 HD_GPIO0_9 Pmod1_1 E Step
125+
IOPortTag & x"00" & HM2DPLLTag & HM2DPLLRefOutPin, -- I/O 10 HD_GPIO0_10 Pmod1_2 DPLL Ref Output
126+
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 11 HD_GPIO0_11 Pmod1_3 Input 1 (Quad A)
127+
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 12 HD_GPIO0_12 Pmod1_4 Input 2 (Quad B)
128+
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 13 HD_GPIO0_13 Pmod1_5 Input 3 (Quad Idx)
129+
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 14 HD_GPIO0_14 Pmod1_6 PWM
130+
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 15 HD_GPIO0_15 Pmod1_7 PWM
131+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 16 HD_GPIO0_16 Ardui_0 GPIO
132+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 17 HD_GPIO0_17 Ardui_1 GPIO
133+
134+
-- Base func sec unit sec func sec pin -- hostmot2 Header Pin Func
135+
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 18 SD_GPIO0_33 Ardui_2 Input 1 (Quad A)
136+
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 19 SD_GPIO0_34 Ardui_3 Input 2 (Quad B)
137+
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 20 SD_GPIO0_35 Ardui_4 Input 3 (Quad Idx)
138+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 21 HD_GPIO0_16 Ardui_5 GPIO
139+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 22 SD_GPIO0_28 Ardui_6 GPIO
140+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 23 SD_GPIO0_28 Ardui_7 GPIO
141+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 SD_GPIO0_28 Ardui_8 GPIO
142+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 25 SD_GPIO0_28 Ardui_9 GPIO
143+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 26 SD_GPIO0_28 Ardui_10 GPIO
144+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 27 SD_GPIO0_28 Ardui_11 GPIO
145+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 28 SD_GPIO0_28 Ardui_12 GPIO
146+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 29 SD_GPIO0_28 Ardui_13 GPIO
147+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 SD_GPIO0_28 Ardui_14 GPIO
148+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 SD_GPIO0_29 Ardui_15 GPIO
149+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 SD_GPIO0_30 FM_J21_0 GPIO
150+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 33 SD_GPIO0_31 FM_J21_1 GPIO
151+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 34 SD_GPIO0_32 FM_J21_2 GPIO
152+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 35 SD_GPIO0_32 FM_J21_3 GPIO
153+
154+
-- Fill remaining 144 pins
155+
emptypin,emptypin,emptypin,emptypin,
156+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
157+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
158+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
159+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
160+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
161+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
162+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
163+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
164+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
165+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
166+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
167+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
168+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
169+
170+
end package PIN_ULTRAMYIR_36;

‎HW/VivadoProjects/myirtech/ultramyir/const/ultramyir_pinmap.xdc‎

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1+
#fan pwm control
2+
#set_property PACKAGE_PIN AD14 [get_ports {FAN_PWM}]
3+
#set_property IOSTANDARD LVCMOS18 [get_ports FAN_PWM]
4+
5+
#######################################################################
6+
# Ultra96 MESA Hostmot2 Signals
7+
#######################################################################
8+
#Pmod0
9+
set_property PACKAGE_PIN J4 [get_ports {IOBits[0]}]; # "J4.IO_L19N_T3L_N1_DBC_AD9N_65"
10+
set_property PACKAGE_PIN J5 [get_ports {IOBits[1]}]; # "J5.IO_L19P_T3L_N0_DBC_AD9P_65"
11+
set_property PACKAGE_PIN N8 [get_ports {IOBits[2]}]; # "N8.IO_L17N_T2U_N9_AD10N_65"
12+
set_property PACKAGE_PIN N9 [get_ports {IOBits[3]}]; # "N9.IO_L17P_T2U_N8_AD10P_65"
13+
set_property PACKAGE_PIN J9 [get_ports {IOBits[4]}]; # "j9.IO_L23N_T3U_N9_65"
14+
set_property PACKAGE_PIN K9 [get_ports {IOBits[5]}]; # "K9.IO_L23P_T3U_N8_I2C_SCLK_65"
15+
set_property PACKAGE_PIN H6 [get_ports {IOBits[6]}]; # "H6.IO_L20N_T3L_N3_AD1N_65"
16+
set_property PACKAGE_PIN J6 [get_ports {IOBits[7]}]; # "J6.IO_L20P_T3L_N2_AD1P_65"
17+
#Pmod1
18+
set_property PACKAGE_PIN AD4 [get_ports {IOBits[8]}]; # "AD4.IO_L13N_T2L_N1_GC_QBC_64"
19+
set_property PACKAGE_PIN AD5 [get_ports {IOBits[9]}]; # "AD5.IO_L13P_T2L_N0_GC_QBC_64"
20+
set_property PACKAGE_PIN AH3 [get_ports {IOBits[10]}]; # "AH3.IO_L20N_T3L_N3_AD1N_64"
21+
set_property PACKAGE_PIN AH1 [get_ports {IOBits[11]}]; # "AH1.IO_L23N_T3U_N9_64"
22+
set_property PACKAGE_PIN AE3 [get_ports {IOBits[12]}]; # "AE3.IO_L21P_T3L_N4_AD8P_64"
23+
set_property PACKAGE_PIN AH4 [get_ports {IOBits[13]}]; # "AH4.IO_L19N_T3L_N1_DBC_AD9N_64"
24+
set_property PACKAGE_PIN AC1 [get_ports {IOBits[14]}]; # "AC1.IO_L18N_T2U_N11_AD2N_64"
25+
set_property PACKAGE_PIN AF3 [get_ports {IOBits[15]}]; # "AF3.IO_L21N_T3L_N5_AD8N_64"
26+
# Arduino
27+
set_property PACKAGE_PIN K8 [get_ports {IOBits[16]}]; # "K8.IO_L22P_T3U_N6_DBC_AD0P_65"
28+
set_property PACKAGE_PIN AH2 [get_ports {IOBits[17]}]; # "AH2.IO_L23P_T3U_N8_64"
29+
set_property PACKAGE_PIN AF2 [get_ports {IOBits[18]}]; # "AF2.IO_L22N_T3U_N7_DBC_AD0N_64"
30+
set_property PACKAGE_PIN AE2 [get_ports {IOBits[19]}]; # "AE2.IO_L22P_T3U_N6_DBC_AD0P_64"
31+
set_property PACKAGE_PIN L8 [get_ports {IOBits[20]}]; # "L8.IO_L18N_T2U_N11_AD2N_65"
32+
set_property PACKAGE_PIN M8 [get_ports {IOBits[21]}]; # "M8.IO_L18P_T2U_N10_AD2P_65"
33+
set_property PACKAGE_PIN AG1 [get_ports {IOBits[22]}]; # "AG1.IO_L24N_T3U_N11_64"
34+
set_property PACKAGE_PIN AF1 [get_ports {IOBits[23]}]; # "AF1.IO_L24P_T3U_N10_64"
35+
set_property PACKAGE_PIN L5 [get_ports {IOBits[24]}]; # "L5.IO_L14N_T2L_N3_GC_65"
36+
set_property PACKAGE_PIN M6 [get_ports {IOBits[25]}]; # "M6.IO_L14P_T2L_N2_GC_65"
37+
set_property PACKAGE_PIN P6 [get_ports {IOBits[26]}]; # "P6.IO_L16N_T2U_N7_QBC_AD3N_65"
38+
set_property PACKAGE_PIN P7 [get_ports {IOBits[27]}]; # "P7.IO_L16P_T2U_N6_QBC_AD3P_65"
39+
set_property PACKAGE_PIN L6 [get_ports {IOBits[28]}]; # "L6.IO_L13N_T2L_N1_GC_QBC_65"
40+
set_property PACKAGE_PIN E1 [get_ports {IOBits[29]}]; # "E1.IO_L13P_T2L_N0_GC_QBC_65"
41+
set_property PACKAGE_PIN N6 [get_ports {IOBits[30]}]; # "N6.IO_L15N_T2L_N5_AD11N_65"
42+
set_property PACKAGE_PIN N7 [get_ports {IOBits[31]}]; # "N7.IO_L15P_T2L_N4_AD11P_65"
43+
#Led
44+
set_property PACKAGE_PIN K7 [get_ports {LED[0]}]; # "K7.IO_L22N_T3U_N7_DBC_AD0N_65"
45+
#FMC Debug J20
46+
set_property PACKAGE_PIN G6 [get_ports {IOBits[32]}]; # "G6.IO_L15P_T2L_N4_AD11P_66"
47+
set_property PACKAGE_PIN K2 [get_ports {IOBits[33]}]; # "K2.IO_L9P_T1L_N4_AD12P_65"
48+
set_property PACKAGE_PIN F6 [get_ports {IOBits[34]}]; # "F6.IO_L15N_T2L_N5_AD11N_66 "
49+
set_property PACKAGE_PIN J2 [get_ports {IOBits[35]}]; # "J2.IO_L9N_T1L_N5_AD12N_65"
50+
set_property PACKAGE_PIN G8 [get_ports {RATES[0]}]; # "G8.IO_L16P_T2U_N6_QBC_AD3P_66"
51+
set_property PACKAGE_PIN R7 [get_ports {RATES[1]}]; # "R7.IO_L5P_T0U_N8_AD14P_65"
52+
set_property PACKAGE_PIN F7 [get_ports {RATES[2]}]; # "F7.IO_L16N_T2U_N7_QBC_AD3N_66"
53+
set_property PACKAGE_PIN T7 [get_ports {RATES[3]}]; # "T7.IO_L5N_T0U_N9_AD14N_65"
54+
set_property PACKAGE_PIN F8 [get_ports {RATES[4]}]; # "F8.IO_L17P_T2U_N8_AD10P_66"
55+
56+
# Set the bank voltage for IO Bank 25 to 3.3V
57+
#set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 25]]
58+
59+
# Set the bank voltage for IO Bank 26 to 3.3V
60+
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 64]]
61+
62+
# Set the bank voltage for IO Bank 65 to 1.8V
63+
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 65]]
64+
65+
# Set the bank voltage for IO Bank 66 to 1.8V
66+
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 66]]

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