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lines changed Original file line number Diff line number Diff line change 1+ #! /bin/sh
2+
3+ # TCL Template Filename
4+ TCL_TEMP_FILE=../../zynq_bp.tcl.in
5+
6+ # The fpga device we are building for
7+ FPGA_DEVICE=xczu3eg-sbva484-1-e
8+ FPGA_DEV_SHORT=Xczu3g
9+
10+ # Base Project Name
11+ PRJ_NAME=ultra96_v2_" $FPGA_DEV_SHORT "
12+
13+ # The board part file url, if the target has one
14+ BOARD_PART=" em.avnet.com:ultra96v2:part0:1.0"
15+
16+ # The physical package pin constraint file
17+ PIN_HW_XDC_FILE=const/ultra96_pinmap.xdc
18+
19+ # The filename of the top level block diagram
20+ TOP_LEVEL_BD_FILE=scripts/soc_system.tcl
21+
22+ # # HostMot2 Pin constraints - these update the IP. Physical pin constraints
23+ # belong in an xdc file above
24+
25+ # HM2 Pin Filename relative to project folder
26+ PIN_FILE=const/PIN_ULTR_36.vhd
27+ # Pin package name defined in above pin file
28+ PIN_NAME=PIN_ULTR_36
29+ # FWID File name in the const folder
30+ FWID_NAME=FWID_ULTRA96_36
31+
32+ # ###########################################################################
33+ # HostMot2 Generic Parameters, autofills IP correctly without regenerating
34+ # block diagram script
35+ # ###########################################################################
36+
37+ # The name of the board to compile into the IP. Matches board name in hal files
38+ BOARD_NAME_HIGH_HEX=52544C55 # ULTR
39+ BOARD_NAME_LOW_HEX=544E5641 # AVNT
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