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the-snowwhitethe-snowwhite
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Correct qsys external signals
Signed-off-by: Michael Brown <producer@holotronic.dk>
1 parent 1a812a8 commit 30720d7

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5 files changed

+19
-107
lines changed

5 files changed

+19
-107
lines changed

‎HW/QuartusProjects/DE0_Nano_SoC_DB25/DE0_Nano_SoC_DB25.vhd‎

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -275,14 +275,7 @@ begin
275275
-- mk_io_hm2_we => hm_chipsel, -- .hm2_chipsel
276276
mk_io_hm2_int_in => irq, -- .hm2_int_in
277277
clk_100mhz_out_clk => hm_clk_med, -- clk_100mhz_out.clk
278-
clk_200mhz_out_clk => hm_clk_high, -- clk_100mhz_out.clk
279-
adc_io_convst => ADC_CONVST, -- adc.CONVST
280-
adc_io_sck => ADC_SCK, -- .SCK
281-
adc_io_sdi => ADC_SDI, -- .SDI
282-
adc_io_sdo => ADC_SDO -- .SDO
283-
-- axi_str_data => out_data[7:0], -- stream_port.data
284-
-- axi_str_valid => out_data[8], -- .valid
285-
-- axi_str_ready => ar_in_sig[1]) -- .ready
278+
clk_200mhz_out_clk => hm_clk_high -- clk_100mhz_out.clk
286279
);
287280

288281
-- Debounce logic to clean out glitches within 1ms

‎HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system_pkg.vhd‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,6 @@ package soc_pkg is
55
-- From: soc_system/soc_system.cmp
66
component soc_system is
77
port (
8-
adc_io_convst : out std_logic; -- convst
9-
adc_io_sck : out std_logic; -- sck
10-
adc_io_sdi : out std_logic; -- sdi
11-
adc_io_sdo : in std_logic := 'X'; -- sdo
128
button_pio_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
139
clk_clk : in std_logic := 'X'; -- clk
1410
clk_100mhz_out_clk : out std_logic; -- clk

‎HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system.qsys‎

Lines changed: 15 additions & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -427,6 +427,11 @@
427427
<interface name="hps_0_f2h_debug_reset_req" internal="hps_0.f2h_debug_reset_req" />
428428
<interface name="hps_0_f2h_stm_hw_events" internal="hps_0.f2h_stm_hw_events" />
429429
<interface name="hps_0_f2h_warm_reset_req" internal="hps_0.f2h_warm_reset_req" />
430+
<interface
431+
name="hps_0_h2f_reset"
432+
internal="hps_0.h2f_reset"
433+
type="reset"
434+
dir="start" />
430435
<interface name="hps_0_hps_io" internal="hps_0.hps_io" type="conduit" dir="end" />
431436
<interface name="lcd_clk" internal="pll_lcd.outclk1" type="clock" dir="start" />
432437
<interface
@@ -1760,77 +1765,6 @@
17601765
version="15.1"
17611766
start="clk_0.clk_reset"
17621767
end="intr_capturer_0.reset_sink" />
1763-
<connection
1764-
kind="reset"
1765-
version="15.1"
1766-
start="hps_0.h2f_reset"
1767-
end="fpga_only_master.clk_reset" />
1768-
<connection
1769-
kind="reset"
1770-
version="15.1"
1771-
start="hps_0.h2f_reset"
1772-
end="hps_only_master.clk_reset" />
1773-
<connection
1774-
kind="reset"
1775-
version="15.1"
1776-
start="hps_0.h2f_reset"
1777-
end="alt_vip_vfr_hdmi.clock_master_reset" />
1778-
<connection
1779-
kind="reset"
1780-
version="15.1"
1781-
start="hps_0.h2f_reset"
1782-
end="alt_vip_vfr_hdmi.clock_reset_reset" />
1783-
<connection
1784-
kind="reset"
1785-
version="15.1"
1786-
start="hps_0.h2f_reset"
1787-
end="alt_vip_itc_0.is_clk_rst_reset" />
1788-
<connection
1789-
kind="reset"
1790-
version="15.1"
1791-
start="hps_0.h2f_reset"
1792-
end="button_pio.reset" />
1793-
<connection
1794-
kind="reset"
1795-
version="15.1"
1796-
start="hps_0.h2f_reset"
1797-
end="dipsw_pio.reset" />
1798-
<connection
1799-
kind="reset"
1800-
version="15.1"
1801-
start="hps_0.h2f_reset"
1802-
end="hm2reg_io_0.reset" />
1803-
<connection
1804-
kind="reset"
1805-
version="15.1"
1806-
start="hps_0.h2f_reset"
1807-
end="jtag_uart.reset" />
1808-
<connection
1809-
kind="reset"
1810-
version="15.1"
1811-
start="hps_0.h2f_reset"
1812-
end="led_pio.reset" />
1813-
<connection
1814-
kind="reset"
1815-
version="15.1"
1816-
start="hps_0.h2f_reset"
1817-
end="mm_bridge_0.reset" />
1818-
<connection
1819-
kind="reset"
1820-
version="15.1"
1821-
start="hps_0.h2f_reset"
1822-
end="pll_lcd.reset" />
1823-
<connection
1824-
kind="reset"
1825-
version="15.1"
1826-
start="hps_0.h2f_reset"
1827-
end="sysid_qsys.reset" />
1828-
<connection kind="reset" version="15.1" start="hps_0.h2f_reset" end="ILC.reset_n" />
1829-
<connection
1830-
kind="reset"
1831-
version="15.1"
1832-
start="hps_0.h2f_reset"
1833-
end="intr_capturer_0.reset_sink" />
18341768
<connection
18351769
kind="reset"
18361770
version="15.1"
@@ -1881,11 +1815,6 @@
18811815
version="15.1"
18821816
start="hps_only_master.master_reset"
18831817
end="alt_vip_itc_0.is_clk_rst_reset" />
1884-
<connection
1885-
kind="reset"
1886-
version="15.1"
1887-
start="fpga_only_master.master_reset"
1888-
end="hm2reg_io_0.reset" />
18891818
<connection
18901819
kind="reset"
18911820
version="15.1"
@@ -1906,11 +1835,6 @@
19061835
version="15.1"
19071836
start="hps_only_master.master_reset"
19081837
end="dipsw_pio.reset" />
1909-
<connection
1910-
kind="reset"
1911-
version="15.1"
1912-
start="hps_only_master.master_reset"
1913-
end="hm2reg_io_0.reset" />
19141838
<connection
19151839
kind="reset"
19161840
version="15.1"
@@ -1961,6 +1885,16 @@
19611885
version="15.1"
19621886
start="hps_only_master.master_reset"
19631887
end="sysid_qsys.reset" />
1888+
<connection
1889+
kind="reset"
1890+
version="15.1"
1891+
start="hps_only_master.master_reset"
1892+
end="hm2reg_io_0.reset" />
1893+
<connection
1894+
kind="reset"
1895+
version="15.1"
1896+
start="fpga_only_master.master_reset"
1897+
end="hm2reg_io_0.reset" />
19641898
<connection
19651899
kind="reset"
19661900
version="15.1"

‎HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/DE10_Nano_SoC_FB_DB25.vhd‎

Lines changed: 3 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ entity DE10_Nano_SoC_FB_DB25 is
5252
HDMI_TX_HS : out std_logic;
5353
HDMI_TX_INT : in std_logic;
5454
HDMI_TX_VS : out std_logic;
55-
55+
5656
--------- ADC ---------
5757
ADC_CONVST : out std_logic;
5858
ADC_SCK : out std_logic;
@@ -291,13 +291,6 @@ begin
291291
mk_io_hm2_int_in => irq, -- .hm2_int_in
292292
clk_100mhz_out_clk => hm_clk_med, -- clk_100mhz_out.clk
293293
clk_200mhz_out_clk => hm_clk_high, -- clk_100mhz_out.clk
294-
adc_io_convst => ADC_CONVST, -- adc.CONVST
295-
adc_io_sck => ADC_SCK, -- .SCK
296-
adc_io_sdi => ADC_SDI, -- .SDI
297-
adc_io_sdo => ADC_SDO, -- .SDO
298-
-- axi_str_data => out_data[7:0], -- stream_port.data
299-
-- axi_str_valid => out_data[8], -- .valid
300-
-- axi_str_ready => ar_in_sig[1]) -- .ready
301294
alt_vip_itc_0_clocked_video_vid_clk => lcd_clk, -- alt_vip_itc_0_clocked_video.vid_clk
302295
alt_vip_itc_0_clocked_video_vid_data (23 downto 0) => HDMI_TX_D, -- .vid_data
303296
-- alt_vip_itc_0_clocked_video_underflow => CONNECTED_TO_alt_vip_itc_0_clocked_video_underflow, -- .underflow
@@ -386,12 +379,12 @@ begin
386379

387380
I2C_HDMI_Config_inst : I2C_HDMI_Config
388381
port map (
389-
iCLK => fpga_clk_50,
382+
iCLK => fpga_clk_50,
390383
iRST_N => '1',
391384
I2C_SCLK => HDMI_I2C_SCL,
392385
I2C_SDAT => HDMI_I2C_SDA,
393386
HDMI_TX_INT => HDMI_TX_INT
394-
-- READY =>
387+
-- READY =>
395388
);
396389

397390

‎HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/soc_system_pkg.vhd‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,6 @@ package soc_pkg is
55
-- From: soc_system/soc_system.cmp
66
component soc_system is
77
port (
8-
adc_io_convst : out std_logic; -- convst
9-
adc_io_sck : out std_logic; -- sck
10-
adc_io_sdi : out std_logic; -- sdi
11-
adc_io_sdo : in std_logic := 'X'; -- sdo
128
alt_vip_itc_0_clocked_video_vid_clk : in std_logic := 'X'; -- vid_clk
139
alt_vip_itc_0_clocked_video_vid_data : out std_logic_vector(31 downto 0); -- vid_data
1410
alt_vip_itc_0_clocked_video_underflow : out std_logic; -- underflow

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