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Merge pull request #112 from the-snowwhite/2019.1_u96-ed
2019.1 u96 ed
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‎HW/VivadoProjects/avnet/ultra96/const/PIN_ULTR_36.vhd‎

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library IEEE;
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use IEEE.std_logic_1164.all; -- defines std_logic types
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- Ported to MYIR ZTURN IO Carrier board:
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-- Copyright (C) 2016, Devin Hughes, JD Squared
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-- http://www.jd2.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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use work.IDROMConst.all;
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package PIN_ULTR_36 is
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constant ModuleID : ModuleIDType :=(
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(HM2DPLLTag, x"00", ClockLowTag, x"04", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
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(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
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(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
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(StepGenTag, x"02", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
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(FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask),
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(PWMTag, x"00", ClockHighTag, x"03", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
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(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
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);
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constant PinDesc : PinDescType :=(
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-- Base func sec unit sec func sec pin -- hostmot2 Header Pin Func
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IOPortTag & x"00" & NullTag & NullPin, -- I/O 00 HD_GPIO0_0 03 GPIO
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IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 HD_GPIO0_1 05 GPIO
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IOPortTag & x"00" & NullTag & NullPin, -- I/O 02 HD_GPIO0_2 07 GPIO
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IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 HD_GPIO0_3 09 GPIO
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IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 HD_GPIO0_4 11 A Dir
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IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 05 HD_GPIO0_5 13 A Step
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IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 06 HD_GPIO0_6 29 B Dir
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IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 07 HD_GPIO0_7 31 B Step
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IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 08 HD_GPIO0_8 33 C Dir
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IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 HD_GPIO0_9 16 C Step
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IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 10 HD_GPIO0_10 18 D Dir
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IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 HD_GPIO0_11 20 D Step
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IOPortTag & x"00" & HM2DPLLTag & HM2DPLLRefOutPin, -- I/O 12 HD_GPIO0_12 22 DPLL Ref Output
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IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 13 HD_GPIO0_14 30 Input 1 (Quad A)
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IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 14 HD_GPIO0_14 32 Input 2 (Quad B)
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IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 15 HD_GPIO0_15 34 Input 3 (Quad Idx)
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-- Base func sec unit sec func sec pin -- hostmot2 Header Pin Func
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IOPortTag & x"00" & NullTag & NullPin, -- I/O 16 SD_GPIO0_16 02 GPIO
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IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 17 SD_GPIO0_17 04 PWM
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IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 18 SD_GPIO0_18 08 PWM
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IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 19 SD_GPIO0_19 10 PWM
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IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 20 SD_GPIO0_20 14 E Dir
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IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 21 SD_GPIO0_21 16 E Step
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IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 22 SD_GPIO0_22 20 F Dir
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IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 23 SD_GPIO0_23 22 F Step
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IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 24 SD_GPIO0_24 26 G Dir
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IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 25 SD_GPIO0_25 28 G Step
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IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 26 SD_GPIO0_26 42 H Dir
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IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 27 SD_GPIO0_27 44 H Step
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IOPortTag & x"00" & NullTag & NullPin, -- I/O 28 SD_GPIO0_28 48 GPIO
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IOPortTag & x"00" & NullTag & NullPin, -- I/O 29 SD_GPIO0_29 57 GPIO
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IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 SD_GPIO0_30 47 GPIO
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IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 SD_GPIO0_31 45 GPIO
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IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 SD_GPIO0_32 41 GPIO
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IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 33 SD_GPIO0_33 50 Input 1 (Quad A)
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IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 34 SD_GPIO0_34 54 Input 2 (Quad B)
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IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 35 SD_GPIO0_35 56 Input 3 (Quad Idx)
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-- Fill remaining 144 pins
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
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emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
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end package PIN_ULTR_36;

‎HW/VivadoProjects/avnet/ultra96/const/ultra96_pinmap.xdc‎

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#######################################################################
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# Ultra96 Bluetooth UART Modem Signals
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#######################################################################
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set_property IOSTANDARD LVCMOS18 [get_ports bt*]
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#BT_HCI_RTS on Ultra96 / emio_uart0_ctsn
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set_property PACKAGE_PIN B7 [get_ports bt_ctsn]
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#BT_HCI_CTS on Ultra96 / emio_uart0_rtsn
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set_property PACKAGE_PIN B5 [get_ports bt_rtsn]
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## Fan signal:
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set_property PACKAGE_PIN F4 [get_ports {FAN_PWM}]; # "F4.FAN_PWM"
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#######################################################################
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# Ultra96 MESA Hostmot2 Signals
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#######################################################################
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set_property PACKAGE_PIN D7 [get_ports {IOBits[0]}]; # "D7.HD_GPIO_0"
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set_property PACKAGE_PIN F8 [get_ports {IOBits[1]}]; # "F8.HD_GPIO_1"
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set_property PACKAGE_PIN F7 [get_ports {IOBits[2]}]; # "F7.HD_GPIO_2"
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set_property PACKAGE_PIN G7 [get_ports {IOBits[3]}]; # "G7.HD_GPIO_3"
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set_property PACKAGE_PIN F6 [get_ports {IOBits[4]}]; # "F6.HD_GPIO_4"
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set_property PACKAGE_PIN G5 [get_ports {IOBits[5]}]; # "G5.HD_GPIO_5"
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set_property PACKAGE_PIN A6 [get_ports {IOBits[6]}]; # "A6.HD_GPIO_6"
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set_property PACKAGE_PIN A7 [get_ports {IOBits[7]}]; # "A7.HD_GPIO_7"
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set_property PACKAGE_PIN G6 [get_ports {IOBits[8]}]; # "G6.HD_GPIO_8"
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set_property PACKAGE_PIN E6 [get_ports {IOBits[9]}]; # "E6.HD_GPIO_9"
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set_property PACKAGE_PIN E5 [get_ports {IOBits[10]}]; # "E5.HD_GPIO_10"
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set_property PACKAGE_PIN D6 [get_ports {IOBits[11]}]; # "D6.HD_GPIO_11"
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set_property PACKAGE_PIN D5 [get_ports {IOBits[12]}]; # "D5.HD_GPIO_12"
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set_property PACKAGE_PIN C7 [get_ports {IOBits[13]}]; # "C7.HD_GPIO_13"
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set_property PACKAGE_PIN B6 [get_ports {IOBits[14]}]; # "B6.HD_GPIO_14"
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set_property PACKAGE_PIN C5 [get_ports {IOBits[15]}]; # "C5.HD_GPIO_15"
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set_property PACKAGE_PIN N2 [get_ports {IOBits[16]}]; # "N2.CSI0_C_P"
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set_property PACKAGE_PIN P1 [get_ports {IOBits[17]}]; # "P1.CSI0_C_N"
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set_property PACKAGE_PIN N5 [get_ports {IOBits[18]}]; # "N5.CSI0_D0_P"
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set_property PACKAGE_PIN N4 [get_ports {IOBits[19]}]; # "N4.CSI0_D0_N"
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set_property PACKAGE_PIN M2 [get_ports {IOBits[20]}]; # "M2.CSI0_D1_P"
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set_property PACKAGE_PIN M1 [get_ports {IOBits[21]}]; # "M1.CSI0_D1_N"
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set_property PACKAGE_PIN M5 [get_ports {IOBits[22]}]; # "M5.CSI0_D2_P"
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set_property PACKAGE_PIN M4 [get_ports {IOBits[23]}]; # "M4.CSI0_D2_N"
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set_property PACKAGE_PIN L2 [get_ports {IOBits[24]}]; # "L2.CSI0_D3_P"
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set_property PACKAGE_PIN L1 [get_ports {IOBits[25]}]; # "L1.CSI0_D3_N"
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set_property PACKAGE_PIN P3 [get_ports {IOBits[26]}]; # "P3.CSI1_D0_P"
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set_property PACKAGE_PIN R3 [get_ports {IOBits[27]}]; # "R3.CSI1_D0_N"
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set_property PACKAGE_PIN U2 [get_ports {IOBits[28]}]; # "U2.CSI1_D1_P"
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set_property PACKAGE_PIN U1 [get_ports {IOBits[29]}]; # "U1.CSI1_D1_N"
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set_property PACKAGE_PIN T3 [get_ports {IOBits[30]}]; # "T3.CSI1_C_P"
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set_property PACKAGE_PIN T2 [get_ports {IOBits[31]}]; # "T2.CSI1_C_N"
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set_property PACKAGE_PIN C2 [get_ports {LED[0]}]; # "C2.HSIC_DATA"
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set_property PACKAGE_PIN A2 [get_ports {IOBits[32]}]; # "A2.HSIC_STR"
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set_property PACKAGE_PIN C3 [get_ports {IOBits[33]}]; # "C3.DSI_D3_N"
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set_property PACKAGE_PIN D3 [get_ports {IOBits[34]}]; # "D3.DSI_D3_P"
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set_property PACKAGE_PIN D1 [get_ports {IOBits[35]}]; # "D1.DSI_D2_N"
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set_property PACKAGE_PIN E1 [get_ports {RATES[0]}]; # "E1.DSI_D2_P"
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set_property PACKAGE_PIN E3 [get_ports {RATES[1]}]; # "E3.DSI_D1_N"
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set_property PACKAGE_PIN E4 [get_ports {RATES[2]}]; # "E4.DSI_D1_P"
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set_property PACKAGE_PIN F1 [get_ports {RATES[3]}]; # "F1.DSI_D0_N"
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set_property PACKAGE_PIN G1 [get_ports {RATES[4]}]; # "G1.DSI_D0_P"
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# Set the bank voltage for IO Bank 26 to 1.8V
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set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 26]]
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# Set the bank voltage for IO Bank 65 to 1.2V
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set_property IOSTANDARD LVCMOS12 [get_ports -of_objects [get_iobanks 65]]
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# Set the bank voltage for IO Bank 66 to 1.2V
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set_property IOSTANDARD LVCMOS12 [get_ports -of_objects [get_iobanks 66]]

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