@@ -80,6 +80,7 @@ parameter NumGPIO = 2;
8080parameter Capsense = 1 ;
8181parameter NumSense = 4 ;
8282parameter ADC = " " ;
83+ parameter Mux_En = 1 ;
8384// local param
8485parameter IoRegWidth = 24 ;
8586parameter AdcOutShift = 2 ;
@@ -154,12 +155,12 @@ parameter TotalNumregs = Mux_regPrIOReg * NumIOAddrReg * NumPinsPrIOAddr;
154155 wire [NumSense- 1 : 0 ] sense;
155156 wire charge;
156157 wire [3 : 0 ] hysteresis[NumSense- 1 : 0 ];
157-
158- wire sr_delay_act;
159- wire sr_init_delay_act;
158+
159+ wire sr_delay_act;
160+ wire sr_init_delay_act;
160161 wire sense_reset;
161162// wire sense_reset = ~reset_reg_N;
162-
163+
163164 genvar sh;
164165 generate
165166 for (sh= 0 ;sh< NumSense;sh= sh+ 1 ) begin : sense_hystloop
@@ -268,14 +269,14 @@ generate if (Capsense >= 1) begin
268269 end
269270 else if ( write_address ) begin
270271 if (busaddress_r == 10'h0304 ) begin
271- hysteresis_reg <= busdata_in_r;
272+ hysteresis_reg <= busdata_in_r;
272273 reset_sr <= 1'b1 ;
273- end
274+ end
274275 else begin
275- hysteresis_reg <= hysteresis_reg;
276+ hysteresis_reg <= hysteresis_reg;
276277 reset_sr <= 1'b0 ;
277278 end
278- end
279+ end
279280 end
280281end
281282endgenerate
@@ -287,11 +288,11 @@ endgenerate
287288 sr_init_delay[1 ] <= sr_init_delay[0 ];
288289 sr_init_delay[2 ] <= sr_init_delay[1 ];
289290 end
290-
291+
291292 assign sr_delay_act = (sr_delay[1 ] == 1'b1 && sr_delay[0 ] == 1'b0 ) ? 1'b1 : 1'b0 ;
292293 assign sr_init_delay_act = (sr_init_delay[2 ] == 1'b0 && sr_init_delay[0 ] == 1'b1 ) ? 1'b1 : 1'b0 ;
293294 assign sense_reset = ~ reset_reg_N | ~ buttons[1 ] | sr_delay_act | sr_init_delay_act;
294-
295+
295296 genvar il;
296297 generate
297298 for (il= 0 ;il< NumIOAddrReg;il= il+ 1 ) begin : reg_initloop
@@ -351,7 +352,7 @@ endgenerate
351352// wire [GPIOWidth-1:0] gpio1_input_data;
352353// assign gpio_input_data[1] = {gpio1_input_data[GPIOWidth-1:5],sense,charge};
353354generate if (Capsense >= 1 ) begin
354- bidir_io # (.IOWidth (GPIOWidth * NumGPIO),.PortNumWidth (PortNumWidth)) bidir_io_inst
355+ bidir_io # (.IOWidth (GPIOWidth * NumGPIO),.PortNumWidth (PortNumWidth),. Mux_En (Mux_En) ) bidir_io_inst
355356 (
356357 .clk (reg_clk),
357358 .portselnum (portnumsel),
@@ -363,7 +364,7 @@ generate if (Capsense >=1) begin
363364 );
364365 end
365366 else begin
366- bidir_io # (.IOWidth (GPIOWidth * NumGPIO),.PortNumWidth (PortNumWidth)) bidir_io_inst
367+ bidir_io # (.IOWidth (GPIOWidth * NumGPIO),.PortNumWidth (PortNumWidth),. Mux_En (Mux_En) ) bidir_io_inst
367368 (
368369 .clk (reg_clk),
369370 .portselnum (portnumsel),
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