CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo #158224
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arsenm
added
backend:AArch64
backend:AMDGPU
backend:ARM
backend:Hexagon
backend:loongarch
backend:MIPS
backend:MSP430
backend:PowerPC
backend:RISC-V
backend:Sparc
backend:SystemZ
backend:WebAssembly
backend:X86
llvm:codegen
llvm:globalisel
llvm:regalloc
llvm:SelectionDAG
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@llvm/pr-subscribers-backend-nvptx @llvm/pr-subscribers-backend-risc-v Author: Matt Arsenault (arsenm) ChangesBoth conceptually belong to the same subtarget, so it should not Most targets placed their TargetRegisterInfo as a member Patch is 45.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/158224.diff 50 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 6a624a7052cdd..802cca6022074 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -113,9 +113,12 @@ struct ExtAddrMode {
///
class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
protected:
- TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
- unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
- : CallFrameSetupOpcode(CFSetupOpcode),
+ const TargetRegisterInfo &TRI;
+
+ TargetInstrInfo(const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u,
+ unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u,
+ unsigned ReturnOpcode = ~0u)
+ : TRI(TRI), CallFrameSetupOpcode(CFSetupOpcode),
CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
ReturnOpcode(ReturnOpcode) {}
@@ -124,6 +127,8 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
virtual ~TargetInstrInfo();
+ const TargetRegisterInfo &getRegisterInfo() const { return TRI; }
+
static bool isGenericOpcode(unsigned Opc) {
return Opc <= TargetOpcode::GENERIC_OP_END;
}
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index b0009560d3fcb..e186932d88309 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -60,20 +60,20 @@ TargetInstrInfo::~TargetInstrInfo() = default;
const TargetRegisterClass *
TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
- const TargetRegisterInfo *TRI) const {
+ const TargetRegisterInfo * /*RemoveMe*/) const {
if (OpNum >= MCID.getNumOperands())
return nullptr;
short RegClass = MCID.operands()[OpNum].RegClass;
if (MCID.operands()[OpNum].isLookupPtrRegClass())
- return TRI->getPointerRegClass(RegClass);
+ return TRI.getPointerRegClass(RegClass);
// Instructions like INSERT_SUBREG do not have fixed register classes.
if (RegClass < 0)
return nullptr;
// Otherwise just look it up normally.
- return TRI->getRegClass(RegClass);
+ return TRI.getRegClass(RegClass);
}
/// insertNoop - Insert a noop into the instruction stream at the specified
@@ -220,13 +220,11 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
// %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
SmallVector<unsigned> UpdateImplicitDefIdx;
if (HasDef && MI.hasImplicitDef()) {
- const TargetRegisterInfo *TRI =
- MI.getMF()->getSubtarget().getRegisterInfo();
for (auto [OpNo, MO] : llvm::enumerate(MI.implicit_operands())) {
Register ImplReg = MO.getReg();
if ((ImplReg.isVirtual() && ImplReg == Reg0) ||
(ImplReg.isPhysical() && Reg0.isPhysical() &&
- TRI->isSubRegisterEq(ImplReg, Reg0)))
+ TRI.isSubRegisterEq(ImplReg, Reg0)))
UpdateImplicitDefIdx.push_back(OpNo + MI.getNumExplicitOperands());
}
}
@@ -422,37 +420,35 @@ bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
unsigned SubIdx, unsigned &Size,
unsigned &Offset,
const MachineFunction &MF) const {
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (!SubIdx) {
- Size = TRI->getSpillSize(*RC);
+ Size = TRI.getSpillSize(*RC);
Offset = 0;
return true;
}
- unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
+ unsigned BitSize = TRI.getSubRegIdxSize(SubIdx);
// Convert bit size to byte size.
if (BitSize % 8)
return false;
- int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
+ int BitOffset = TRI.getSubRegIdxOffset(SubIdx);
if (BitOffset < 0 || BitOffset % 8)
return false;
Size = BitSize / 8;
Offset = (unsigned)BitOffset / 8;
- assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
+ assert(TRI.getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
if (!MF.getDataLayout().isLittleEndian()) {
- Offset = TRI->getSpillSize(*RC) - (Offset + Size);
+ Offset = TRI.getSpillSize(*RC) - (Offset + Size);
}
return true;
}
-void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- Register DestReg, unsigned SubIdx,
- const MachineInstr &Orig,
- const TargetRegisterInfo &TRI) const {
+void TargetInstrInfo::reMaterialize(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
+ unsigned SubIdx, const MachineInstr &Orig,
+ const TargetRegisterInfo & /*Remove me*/) const {
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
MBB.insert(I, MI);
@@ -723,7 +719,6 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
// actual load size is.
int64_t MemSize = 0;
const MachineFrameInfo &MFI = MF.getFrameInfo();
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (Flags & MachineMemOperand::MOStore) {
MemSize = MFI.getObjectSize(FI);
@@ -732,7 +727,7 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
int64_t OpSize = MFI.getObjectSize(FI);
if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {
- unsigned SubRegSize = TRI->getSubRegIdxSize(SubReg);
+ unsigned SubRegSize = TRI.getSubRegIdxSize(SubReg);
if (SubRegSize > 0 && !(SubRegSize % 8))
OpSize = SubRegSize / 8;
}
@@ -797,11 +792,11 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
// code.
BuildMI(*MBB, Pos, MI.getDebugLoc(), get(TargetOpcode::KILL)).add(MO);
} else {
- storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI,
+ storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, &TRI,
Register());
}
} else
- loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI, Register());
+ loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, &TRI, Register());
return &*--Pos;
}
@@ -877,8 +872,8 @@ static void transferImplicitOperands(MachineInstr *MI,
}
}
-void TargetInstrInfo::lowerCopy(MachineInstr *MI,
- const TargetRegisterInfo *TRI) const {
+void TargetInstrInfo::lowerCopy(
+ MachineInstr *MI, const TargetRegisterInfo * /*Remove me*/) const {
if (MI->allDefsAreDead()) {
MI->setDesc(get(TargetOpcode::KILL));
return;
@@ -908,7 +903,7 @@ void TargetInstrInfo::lowerCopy(MachineInstr *MI,
SrcMO.getReg().isPhysical() ? SrcMO.isRenamable() : false);
if (MI->getNumOperands() > 2)
- transferImplicitOperands(MI, TRI);
+ transferImplicitOperands(MI, &TRI);
MI->eraseFromParent();
}
@@ -1324,8 +1319,7 @@ void TargetInstrInfo::reassociateOps(
MachineFunction *MF = Root.getMF();
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
- const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
- const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
+ const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, &TRI);
MachineOperand &OpA = Prev.getOperand(OperandIndices[1]);
MachineOperand &OpB = Root.getOperand(OperandIndices[2]);
@@ -1707,8 +1701,7 @@ bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
// stack slot reference to depend on the instruction that does the
// modification.
const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
+ return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), &TRI);
}
// Provide a global flag for disabling the PreRA hazard recognizer that targets
@@ -1741,11 +1734,11 @@ CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
// Default implementation of getMemOperandWithOffset.
bool TargetInstrInfo::getMemOperandWithOffset(
const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset,
- bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const {
+ bool &OffsetIsScalable, const TargetRegisterInfo * /*RemoveMe*/) const {
SmallVector<const MachineOperand *, 4> BaseOps;
LocationSize Width = LocationSize::precise(0);
if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable,
- Width, TRI) ||
+ Width, &TRI) ||
BaseOps.size() != 1)
return false;
BaseOp = BaseOps.front();
@@ -1866,7 +1859,6 @@ std::optional<ParamLoadedValue>
TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
Register Reg) const {
const MachineFunction *MF = MI.getMF();
- const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
DIExpression *Expr = DIExpression::get(MF->getFunction().getContext(), {});
int64_t Offset;
bool OffsetIsScalable;
@@ -1897,7 +1889,6 @@ TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
// Only describe memory which provably does not escape the function. As
// described in llvm.org/PR43343, escaped memory may be clobbered by the
// callee (or by another thread).
- const auto &TII = MF->getSubtarget().getInstrInfo();
const MachineFrameInfo &MFI = MF->getFrameInfo();
const MachineMemOperand *MMO = MI.memoperands()[0];
const PseudoSourceValue *PSV = MMO->getPseudoValue();
@@ -1908,8 +1899,7 @@ TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
return std::nullopt;
const MachineOperand *BaseOp;
- if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
- TRI))
+ if (!getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, &TRI))
return std::nullopt;
// FIXME: Scalable offsets are not yet handled in the offset code below.
@@ -2048,7 +2038,7 @@ bool TargetInstrInfo::getInsertSubregInputs(
// Returns a MIRPrinter comment for this machine operand.
std::string TargetInstrInfo::createMIROperandComment(
const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
- const TargetRegisterInfo *TRI) const {
+ const TargetRegisterInfo * /*RemoveMe*/) const {
if (!MI.isInlineAsm())
return "";
@@ -2081,12 +2071,8 @@ std::string TargetInstrInfo::createMIROperandComment(
OS << F.getKindName();
unsigned RCID;
- if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) {
- if (TRI) {
- OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
- } else
- OS << ":RC" << RCID;
- }
+ if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID))
+ OS << ':' << TRI.getRegClassName(TRI.getRegClass(RCID));
if (F.isMemKind()) {
InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 9a7512b77ecdb..19f421a4a081b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -91,7 +91,7 @@ static cl::opt<unsigned> GatherOptSearchLimit(
"machine-combiner gather pattern optimization"));
AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
- : AArch64GenInstrInfo(STI, AArch64::ADJCALLSTACKDOWN,
+ : AArch64GenInstrInfo(STI, RI, AArch64::ADJCALLSTACKDOWN,
AArch64::ADJCALLSTACKUP, AArch64::CATCHRET),
RI(STI.getTargetTriple(), STI.getHwMode()), Subtarget(STI) {}
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index 3e256cce97afb..01040854e1577 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -29,7 +29,7 @@ using namespace llvm;
#include "R600GenInstrInfo.inc"
R600InstrInfo::R600InstrInfo(const R600Subtarget &ST)
- : R600GenInstrInfo(ST, -1, -1), RI(), ST(ST) {}
+ : R600GenInstrInfo(ST, RI, -1, -1), RI(), ST(ST) {}
bool R600InstrInfo::isVector(const MachineInstr &MI) const {
return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f06c06dd203b3..1b855248bb1fd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -62,7 +62,8 @@ static cl::opt<bool> Fix16BitCopies(
cl::ReallyHidden);
SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
- : AMDGPUGenInstrInfo(ST, AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
+ : AMDGPUGenInstrInfo(ST, RI, AMDGPU::ADJCALLSTACKUP,
+ AMDGPU::ADJCALLSTACKDOWN),
RI(ST), ST(ST) {
SchedModel.init(&ST);
}
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 05bcb3596ac48..2dec6ffd89a75 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -44,7 +44,8 @@ enum TSFlagsConstants {
void ARCInstrInfo::anchor() {}
ARCInstrInfo::ARCInstrInfo(const ARCSubtarget &ST)
- : ARCGenInstrInfo(ST, ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI(ST) {}
+ : ARCGenInstrInfo(ST, RI, ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP),
+ RI(ST) {}
static bool isZeroImm(const MachineOperand &Op) {
return Op.isImm() && Op.getImm() == 0;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 5c35b3327c16d..b5280812e8b37 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -107,8 +107,9 @@ static const ARM_MLxEntry ARM_MLxTable[] = {
{ ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
};
-ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
- : ARMGenInstrInfo(STI, ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
+ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI,
+ const ARMBaseRegisterInfo &TRI)
+ : ARMGenInstrInfo(STI, TRI, ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
Subtarget(STI) {
for (unsigned i = 0, e = std::size(ARM_MLxTable); i != e; ++i) {
if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 71de3c6ad597a..213333b23ea92 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -44,7 +44,8 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
protected:
// Can be only subclassed.
- explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
+ explicit ARMBaseInstrInfo(const ARMSubtarget &STI,
+ const ARMBaseRegisterInfo &TRI);
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
unsigned LoadImmOpc, unsigned LoadOpc) const;
@@ -125,7 +126,11 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
// if there is not such an opcode.
virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
- virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
+ const ARMBaseRegisterInfo &getRegisterInfo() const {
+ return static_cast<const ARMBaseRegisterInfo &>(
+ TargetInstrInfo::getRegisterInfo());
+ }
+
const ARMSubtarget &getSubtarget() const { return Subtarget; }
ScheduleHazardRecognizer *
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index c684de7252e5d..f37054736b730 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -25,7 +25,8 @@
#include "llvm/MC/MCInst.h"
using namespace llvm;
-ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) : ARMBaseInstrInfo(STI) {}
+ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
+ : ARMBaseInstrInfo(STI, RI) {}
/// Return the noop instruction to use for a noop.
MCInst ARMInstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.h b/llvm/lib/Target/ARM/ARMInstrInfo.h
index 178d7a2c630e4..9feaf1440f2b2 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.h
@@ -35,7 +35,7 @@ class ARMInstrInfo : public ARMBaseInstrInfo {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- const ARMRegisterInfo &getRegisterInfo() const override { return RI; }
+ const ARMRegisterInfo &getRegisterInfo() const { return RI; }
private:
void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index 4b8c2fd569ead..f95ba6a4d86fb 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -24,7 +24,7 @@
using namespace llvm;
Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
- : ARMBaseInstrInfo(STI), RI(STI) {}
+ : ARMBaseInstrInfo(STI, RI), RI(STI) {}
/// Return the noop instruction to use for a noop.
MCInst Thumb1InstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.h b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
index 68b326c0ebef6..16350a65a6198 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
@@ -35,7 +35,7 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
+ const ThumbRegisterInfo &getRegisterInfo() const { return RI; }
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, Register DestReg, Register SrcReg,
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 431ce38ad6e99..9e924e61a5ba5 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -46,7 +46,7 @@ PreferNoCSEL("prefer-no-csel", cl::Hidden,
cl::init(false));
Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
- : ARMBaseInstrInfo(STI), RI(STI) {}
+ : ARMBaseInstrInfo(STI, RI), RI(STI) {}
/// Return the noop instruction to use for a noop.
MCInst Thumb2InstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.h b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
index 3ec3a6216b9f6..3e97fc550cbf9 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
@@ -58,7 +58,7 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
+ const ThumbRegisterInfo &getRegisterInfo() const { return RI; }
MachineInstr *optimizeSelect(MachineInstr &MI,
SmallPtrSetImpl<MachineInstr *> &SeenMIs,
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
index ce9908597dcac..5e247cb64a991 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
@@ -30,8 +30,8 @@
namespace llvm {
AVRInstrInfo::AVRInstrInfo(const AVRSubtarget &STI)
- : AVRGenInstrInfo(STI, AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI(),
- STI(STI) {}
+ : AVRGenInstrInfo(STI, RI, AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP),
+ RI(), STI(STI) {}
void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInst...
[truncated]
|
Member
|
@llvm/pr-subscribers-backend-hexagon Author: Matt Arsenault (arsenm) ChangesBoth conceptually belong to the same subtarget, so it should not Most targets placed their TargetRegisterInfo as a member Patch is 45.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/158224.diff 50 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 6a624a7052cdd..802cca6022074 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -113,9 +113,12 @@ struct ExtAddrMode {
///
class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
protected:
- TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
- unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
- : CallFrameSetupOpcode(CFSetupOpcode),
+ const TargetRegisterInfo &TRI;
+
+ TargetInstrInfo(const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u,
+ unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u,
+ unsigned ReturnOpcode = ~0u)
+ : TRI(TRI), CallFrameSetupOpcode(CFSetupOpcode),
CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
ReturnOpcode(ReturnOpcode) {}
@@ -124,6 +127,8 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
virtual ~TargetInstrInfo();
+ const TargetRegisterInfo &getRegisterInfo() const { return TRI; }
+
static bool isGenericOpcode(unsigned Opc) {
return Opc <= TargetOpcode::GENERIC_OP_END;
}
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index b0009560d3fcb..e186932d88309 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -60,20 +60,20 @@ TargetInstrInfo::~TargetInstrInfo() = default;
const TargetRegisterClass *
TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
- const TargetRegisterInfo *TRI) const {
+ const TargetRegisterInfo * /*RemoveMe*/) const {
if (OpNum >= MCID.getNumOperands())
return nullptr;
short RegClass = MCID.operands()[OpNum].RegClass;
if (MCID.operands()[OpNum].isLookupPtrRegClass())
- return TRI->getPointerRegClass(RegClass);
+ return TRI.getPointerRegClass(RegClass);
// Instructions like INSERT_SUBREG do not have fixed register classes.
if (RegClass < 0)
return nullptr;
// Otherwise just look it up normally.
- return TRI->getRegClass(RegClass);
+ return TRI.getRegClass(RegClass);
}
/// insertNoop - Insert a noop into the instruction stream at the specified
@@ -220,13 +220,11 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
// %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
SmallVector<unsigned> UpdateImplicitDefIdx;
if (HasDef && MI.hasImplicitDef()) {
- const TargetRegisterInfo *TRI =
- MI.getMF()->getSubtarget().getRegisterInfo();
for (auto [OpNo, MO] : llvm::enumerate(MI.implicit_operands())) {
Register ImplReg = MO.getReg();
if ((ImplReg.isVirtual() && ImplReg == Reg0) ||
(ImplReg.isPhysical() && Reg0.isPhysical() &&
- TRI->isSubRegisterEq(ImplReg, Reg0)))
+ TRI.isSubRegisterEq(ImplReg, Reg0)))
UpdateImplicitDefIdx.push_back(OpNo + MI.getNumExplicitOperands());
}
}
@@ -422,37 +420,35 @@ bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
unsigned SubIdx, unsigned &Size,
unsigned &Offset,
const MachineFunction &MF) const {
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (!SubIdx) {
- Size = TRI->getSpillSize(*RC);
+ Size = TRI.getSpillSize(*RC);
Offset = 0;
return true;
}
- unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
+ unsigned BitSize = TRI.getSubRegIdxSize(SubIdx);
// Convert bit size to byte size.
if (BitSize % 8)
return false;
- int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
+ int BitOffset = TRI.getSubRegIdxOffset(SubIdx);
if (BitOffset < 0 || BitOffset % 8)
return false;
Size = BitSize / 8;
Offset = (unsigned)BitOffset / 8;
- assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
+ assert(TRI.getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
if (!MF.getDataLayout().isLittleEndian()) {
- Offset = TRI->getSpillSize(*RC) - (Offset + Size);
+ Offset = TRI.getSpillSize(*RC) - (Offset + Size);
}
return true;
}
-void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- Register DestReg, unsigned SubIdx,
- const MachineInstr &Orig,
- const TargetRegisterInfo &TRI) const {
+void TargetInstrInfo::reMaterialize(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
+ unsigned SubIdx, const MachineInstr &Orig,
+ const TargetRegisterInfo & /*Remove me*/) const {
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
MBB.insert(I, MI);
@@ -723,7 +719,6 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
// actual load size is.
int64_t MemSize = 0;
const MachineFrameInfo &MFI = MF.getFrameInfo();
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (Flags & MachineMemOperand::MOStore) {
MemSize = MFI.getObjectSize(FI);
@@ -732,7 +727,7 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
int64_t OpSize = MFI.getObjectSize(FI);
if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {
- unsigned SubRegSize = TRI->getSubRegIdxSize(SubReg);
+ unsigned SubRegSize = TRI.getSubRegIdxSize(SubReg);
if (SubRegSize > 0 && !(SubRegSize % 8))
OpSize = SubRegSize / 8;
}
@@ -797,11 +792,11 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
// code.
BuildMI(*MBB, Pos, MI.getDebugLoc(), get(TargetOpcode::KILL)).add(MO);
} else {
- storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI,
+ storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, &TRI,
Register());
}
} else
- loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI, Register());
+ loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, &TRI, Register());
return &*--Pos;
}
@@ -877,8 +872,8 @@ static void transferImplicitOperands(MachineInstr *MI,
}
}
-void TargetInstrInfo::lowerCopy(MachineInstr *MI,
- const TargetRegisterInfo *TRI) const {
+void TargetInstrInfo::lowerCopy(
+ MachineInstr *MI, const TargetRegisterInfo * /*Remove me*/) const {
if (MI->allDefsAreDead()) {
MI->setDesc(get(TargetOpcode::KILL));
return;
@@ -908,7 +903,7 @@ void TargetInstrInfo::lowerCopy(MachineInstr *MI,
SrcMO.getReg().isPhysical() ? SrcMO.isRenamable() : false);
if (MI->getNumOperands() > 2)
- transferImplicitOperands(MI, TRI);
+ transferImplicitOperands(MI, &TRI);
MI->eraseFromParent();
}
@@ -1324,8 +1319,7 @@ void TargetInstrInfo::reassociateOps(
MachineFunction *MF = Root.getMF();
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
- const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
- const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
+ const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, &TRI);
MachineOperand &OpA = Prev.getOperand(OperandIndices[1]);
MachineOperand &OpB = Root.getOperand(OperandIndices[2]);
@@ -1707,8 +1701,7 @@ bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
// stack slot reference to depend on the instruction that does the
// modification.
const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
+ return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), &TRI);
}
// Provide a global flag for disabling the PreRA hazard recognizer that targets
@@ -1741,11 +1734,11 @@ CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
// Default implementation of getMemOperandWithOffset.
bool TargetInstrInfo::getMemOperandWithOffset(
const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset,
- bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const {
+ bool &OffsetIsScalable, const TargetRegisterInfo * /*RemoveMe*/) const {
SmallVector<const MachineOperand *, 4> BaseOps;
LocationSize Width = LocationSize::precise(0);
if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable,
- Width, TRI) ||
+ Width, &TRI) ||
BaseOps.size() != 1)
return false;
BaseOp = BaseOps.front();
@@ -1866,7 +1859,6 @@ std::optional<ParamLoadedValue>
TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
Register Reg) const {
const MachineFunction *MF = MI.getMF();
- const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
DIExpression *Expr = DIExpression::get(MF->getFunction().getContext(), {});
int64_t Offset;
bool OffsetIsScalable;
@@ -1897,7 +1889,6 @@ TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
// Only describe memory which provably does not escape the function. As
// described in llvm.org/PR43343, escaped memory may be clobbered by the
// callee (or by another thread).
- const auto &TII = MF->getSubtarget().getInstrInfo();
const MachineFrameInfo &MFI = MF->getFrameInfo();
const MachineMemOperand *MMO = MI.memoperands()[0];
const PseudoSourceValue *PSV = MMO->getPseudoValue();
@@ -1908,8 +1899,7 @@ TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
return std::nullopt;
const MachineOperand *BaseOp;
- if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
- TRI))
+ if (!getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, &TRI))
return std::nullopt;
// FIXME: Scalable offsets are not yet handled in the offset code below.
@@ -2048,7 +2038,7 @@ bool TargetInstrInfo::getInsertSubregInputs(
// Returns a MIRPrinter comment for this machine operand.
std::string TargetInstrInfo::createMIROperandComment(
const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
- const TargetRegisterInfo *TRI) const {
+ const TargetRegisterInfo * /*RemoveMe*/) const {
if (!MI.isInlineAsm())
return "";
@@ -2081,12 +2071,8 @@ std::string TargetInstrInfo::createMIROperandComment(
OS << F.getKindName();
unsigned RCID;
- if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) {
- if (TRI) {
- OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
- } else
- OS << ":RC" << RCID;
- }
+ if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID))
+ OS << ':' << TRI.getRegClassName(TRI.getRegClass(RCID));
if (F.isMemKind()) {
InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 9a7512b77ecdb..19f421a4a081b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -91,7 +91,7 @@ static cl::opt<unsigned> GatherOptSearchLimit(
"machine-combiner gather pattern optimization"));
AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
- : AArch64GenInstrInfo(STI, AArch64::ADJCALLSTACKDOWN,
+ : AArch64GenInstrInfo(STI, RI, AArch64::ADJCALLSTACKDOWN,
AArch64::ADJCALLSTACKUP, AArch64::CATCHRET),
RI(STI.getTargetTriple(), STI.getHwMode()), Subtarget(STI) {}
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index 3e256cce97afb..01040854e1577 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -29,7 +29,7 @@ using namespace llvm;
#include "R600GenInstrInfo.inc"
R600InstrInfo::R600InstrInfo(const R600Subtarget &ST)
- : R600GenInstrInfo(ST, -1, -1), RI(), ST(ST) {}
+ : R600GenInstrInfo(ST, RI, -1, -1), RI(), ST(ST) {}
bool R600InstrInfo::isVector(const MachineInstr &MI) const {
return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f06c06dd203b3..1b855248bb1fd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -62,7 +62,8 @@ static cl::opt<bool> Fix16BitCopies(
cl::ReallyHidden);
SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
- : AMDGPUGenInstrInfo(ST, AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
+ : AMDGPUGenInstrInfo(ST, RI, AMDGPU::ADJCALLSTACKUP,
+ AMDGPU::ADJCALLSTACKDOWN),
RI(ST), ST(ST) {
SchedModel.init(&ST);
}
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 05bcb3596ac48..2dec6ffd89a75 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -44,7 +44,8 @@ enum TSFlagsConstants {
void ARCInstrInfo::anchor() {}
ARCInstrInfo::ARCInstrInfo(const ARCSubtarget &ST)
- : ARCGenInstrInfo(ST, ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI(ST) {}
+ : ARCGenInstrInfo(ST, RI, ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP),
+ RI(ST) {}
static bool isZeroImm(const MachineOperand &Op) {
return Op.isImm() && Op.getImm() == 0;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 5c35b3327c16d..b5280812e8b37 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -107,8 +107,9 @@ static const ARM_MLxEntry ARM_MLxTable[] = {
{ ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
};
-ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
- : ARMGenInstrInfo(STI, ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
+ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI,
+ const ARMBaseRegisterInfo &TRI)
+ : ARMGenInstrInfo(STI, TRI, ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
Subtarget(STI) {
for (unsigned i = 0, e = std::size(ARM_MLxTable); i != e; ++i) {
if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 71de3c6ad597a..213333b23ea92 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -44,7 +44,8 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
protected:
// Can be only subclassed.
- explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
+ explicit ARMBaseInstrInfo(const ARMSubtarget &STI,
+ const ARMBaseRegisterInfo &TRI);
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
unsigned LoadImmOpc, unsigned LoadOpc) const;
@@ -125,7 +126,11 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
// if there is not such an opcode.
virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
- virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
+ const ARMBaseRegisterInfo &getRegisterInfo() const {
+ return static_cast<const ARMBaseRegisterInfo &>(
+ TargetInstrInfo::getRegisterInfo());
+ }
+
const ARMSubtarget &getSubtarget() const { return Subtarget; }
ScheduleHazardRecognizer *
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index c684de7252e5d..f37054736b730 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -25,7 +25,8 @@
#include "llvm/MC/MCInst.h"
using namespace llvm;
-ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) : ARMBaseInstrInfo(STI) {}
+ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
+ : ARMBaseInstrInfo(STI, RI) {}
/// Return the noop instruction to use for a noop.
MCInst ARMInstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.h b/llvm/lib/Target/ARM/ARMInstrInfo.h
index 178d7a2c630e4..9feaf1440f2b2 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.h
@@ -35,7 +35,7 @@ class ARMInstrInfo : public ARMBaseInstrInfo {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- const ARMRegisterInfo &getRegisterInfo() const override { return RI; }
+ const ARMRegisterInfo &getRegisterInfo() const { return RI; }
private:
void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index 4b8c2fd569ead..f95ba6a4d86fb 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -24,7 +24,7 @@
using namespace llvm;
Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
- : ARMBaseInstrInfo(STI), RI(STI) {}
+ : ARMBaseInstrInfo(STI, RI), RI(STI) {}
/// Return the noop instruction to use for a noop.
MCInst Thumb1InstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.h b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
index 68b326c0ebef6..16350a65a6198 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
@@ -35,7 +35,7 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
+ const ThumbRegisterInfo &getRegisterInfo() const { return RI; }
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, Register DestReg, Register SrcReg,
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 431ce38ad6e99..9e924e61a5ba5 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -46,7 +46,7 @@ PreferNoCSEL("prefer-no-csel", cl::Hidden,
cl::init(false));
Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
- : ARMBaseInstrInfo(STI), RI(STI) {}
+ : ARMBaseInstrInfo(STI, RI), RI(STI) {}
/// Return the noop instruction to use for a noop.
MCInst Thumb2InstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.h b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
index 3ec3a6216b9f6..3e97fc550cbf9 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
@@ -58,7 +58,7 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
+ const ThumbRegisterInfo &getRegisterInfo() const { return RI; }
MachineInstr *optimizeSelect(MachineInstr &MI,
SmallPtrSetImpl<MachineInstr *> &SeenMIs,
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
index ce9908597dcac..5e247cb64a991 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
@@ -30,8 +30,8 @@
namespace llvm {
AVRInstrInfo::AVRInstrInfo(const AVRSubtarget &STI)
- : AVRGenInstrInfo(STI, AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI(),
- STI(STI) {}
+ : AVRGenInstrInfo(STI, RI, AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP),
+ RI(), STI(STI) {}
void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInst...
[truncated]
|
Member
|
@llvm/pr-subscribers-backend-msp430 Author: Matt Arsenault (arsenm) ChangesBoth conceptually belong to the same subtarget, so it should not Most targets placed their TargetRegisterInfo as a member Patch is 45.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/158224.diff 50 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 6a624a7052cdd..802cca6022074 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -113,9 +113,12 @@ struct ExtAddrMode {
///
class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
protected:
- TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
- unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
- : CallFrameSetupOpcode(CFSetupOpcode),
+ const TargetRegisterInfo &TRI;
+
+ TargetInstrInfo(const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u,
+ unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u,
+ unsigned ReturnOpcode = ~0u)
+ : TRI(TRI), CallFrameSetupOpcode(CFSetupOpcode),
CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
ReturnOpcode(ReturnOpcode) {}
@@ -124,6 +127,8 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
virtual ~TargetInstrInfo();
+ const TargetRegisterInfo &getRegisterInfo() const { return TRI; }
+
static bool isGenericOpcode(unsigned Opc) {
return Opc <= TargetOpcode::GENERIC_OP_END;
}
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index b0009560d3fcb..e186932d88309 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -60,20 +60,20 @@ TargetInstrInfo::~TargetInstrInfo() = default;
const TargetRegisterClass *
TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
- const TargetRegisterInfo *TRI) const {
+ const TargetRegisterInfo * /*RemoveMe*/) const {
if (OpNum >= MCID.getNumOperands())
return nullptr;
short RegClass = MCID.operands()[OpNum].RegClass;
if (MCID.operands()[OpNum].isLookupPtrRegClass())
- return TRI->getPointerRegClass(RegClass);
+ return TRI.getPointerRegClass(RegClass);
// Instructions like INSERT_SUBREG do not have fixed register classes.
if (RegClass < 0)
return nullptr;
// Otherwise just look it up normally.
- return TRI->getRegClass(RegClass);
+ return TRI.getRegClass(RegClass);
}
/// insertNoop - Insert a noop into the instruction stream at the specified
@@ -220,13 +220,11 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
// %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
SmallVector<unsigned> UpdateImplicitDefIdx;
if (HasDef && MI.hasImplicitDef()) {
- const TargetRegisterInfo *TRI =
- MI.getMF()->getSubtarget().getRegisterInfo();
for (auto [OpNo, MO] : llvm::enumerate(MI.implicit_operands())) {
Register ImplReg = MO.getReg();
if ((ImplReg.isVirtual() && ImplReg == Reg0) ||
(ImplReg.isPhysical() && Reg0.isPhysical() &&
- TRI->isSubRegisterEq(ImplReg, Reg0)))
+ TRI.isSubRegisterEq(ImplReg, Reg0)))
UpdateImplicitDefIdx.push_back(OpNo + MI.getNumExplicitOperands());
}
}
@@ -422,37 +420,35 @@ bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
unsigned SubIdx, unsigned &Size,
unsigned &Offset,
const MachineFunction &MF) const {
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (!SubIdx) {
- Size = TRI->getSpillSize(*RC);
+ Size = TRI.getSpillSize(*RC);
Offset = 0;
return true;
}
- unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
+ unsigned BitSize = TRI.getSubRegIdxSize(SubIdx);
// Convert bit size to byte size.
if (BitSize % 8)
return false;
- int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
+ int BitOffset = TRI.getSubRegIdxOffset(SubIdx);
if (BitOffset < 0 || BitOffset % 8)
return false;
Size = BitSize / 8;
Offset = (unsigned)BitOffset / 8;
- assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
+ assert(TRI.getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
if (!MF.getDataLayout().isLittleEndian()) {
- Offset = TRI->getSpillSize(*RC) - (Offset + Size);
+ Offset = TRI.getSpillSize(*RC) - (Offset + Size);
}
return true;
}
-void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- Register DestReg, unsigned SubIdx,
- const MachineInstr &Orig,
- const TargetRegisterInfo &TRI) const {
+void TargetInstrInfo::reMaterialize(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
+ unsigned SubIdx, const MachineInstr &Orig,
+ const TargetRegisterInfo & /*Remove me*/) const {
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
MBB.insert(I, MI);
@@ -723,7 +719,6 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
// actual load size is.
int64_t MemSize = 0;
const MachineFrameInfo &MFI = MF.getFrameInfo();
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (Flags & MachineMemOperand::MOStore) {
MemSize = MFI.getObjectSize(FI);
@@ -732,7 +727,7 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
int64_t OpSize = MFI.getObjectSize(FI);
if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {
- unsigned SubRegSize = TRI->getSubRegIdxSize(SubReg);
+ unsigned SubRegSize = TRI.getSubRegIdxSize(SubReg);
if (SubRegSize > 0 && !(SubRegSize % 8))
OpSize = SubRegSize / 8;
}
@@ -797,11 +792,11 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
// code.
BuildMI(*MBB, Pos, MI.getDebugLoc(), get(TargetOpcode::KILL)).add(MO);
} else {
- storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI,
+ storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, &TRI,
Register());
}
} else
- loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI, Register());
+ loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, &TRI, Register());
return &*--Pos;
}
@@ -877,8 +872,8 @@ static void transferImplicitOperands(MachineInstr *MI,
}
}
-void TargetInstrInfo::lowerCopy(MachineInstr *MI,
- const TargetRegisterInfo *TRI) const {
+void TargetInstrInfo::lowerCopy(
+ MachineInstr *MI, const TargetRegisterInfo * /*Remove me*/) const {
if (MI->allDefsAreDead()) {
MI->setDesc(get(TargetOpcode::KILL));
return;
@@ -908,7 +903,7 @@ void TargetInstrInfo::lowerCopy(MachineInstr *MI,
SrcMO.getReg().isPhysical() ? SrcMO.isRenamable() : false);
if (MI->getNumOperands() > 2)
- transferImplicitOperands(MI, TRI);
+ transferImplicitOperands(MI, &TRI);
MI->eraseFromParent();
}
@@ -1324,8 +1319,7 @@ void TargetInstrInfo::reassociateOps(
MachineFunction *MF = Root.getMF();
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
- const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
- const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
+ const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, &TRI);
MachineOperand &OpA = Prev.getOperand(OperandIndices[1]);
MachineOperand &OpB = Root.getOperand(OperandIndices[2]);
@@ -1707,8 +1701,7 @@ bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
// stack slot reference to depend on the instruction that does the
// modification.
const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
+ return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), &TRI);
}
// Provide a global flag for disabling the PreRA hazard recognizer that targets
@@ -1741,11 +1734,11 @@ CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
// Default implementation of getMemOperandWithOffset.
bool TargetInstrInfo::getMemOperandWithOffset(
const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset,
- bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const {
+ bool &OffsetIsScalable, const TargetRegisterInfo * /*RemoveMe*/) const {
SmallVector<const MachineOperand *, 4> BaseOps;
LocationSize Width = LocationSize::precise(0);
if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable,
- Width, TRI) ||
+ Width, &TRI) ||
BaseOps.size() != 1)
return false;
BaseOp = BaseOps.front();
@@ -1866,7 +1859,6 @@ std::optional<ParamLoadedValue>
TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
Register Reg) const {
const MachineFunction *MF = MI.getMF();
- const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
DIExpression *Expr = DIExpression::get(MF->getFunction().getContext(), {});
int64_t Offset;
bool OffsetIsScalable;
@@ -1897,7 +1889,6 @@ TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
// Only describe memory which provably does not escape the function. As
// described in llvm.org/PR43343, escaped memory may be clobbered by the
// callee (or by another thread).
- const auto &TII = MF->getSubtarget().getInstrInfo();
const MachineFrameInfo &MFI = MF->getFrameInfo();
const MachineMemOperand *MMO = MI.memoperands()[0];
const PseudoSourceValue *PSV = MMO->getPseudoValue();
@@ -1908,8 +1899,7 @@ TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
return std::nullopt;
const MachineOperand *BaseOp;
- if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
- TRI))
+ if (!getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, &TRI))
return std::nullopt;
// FIXME: Scalable offsets are not yet handled in the offset code below.
@@ -2048,7 +2038,7 @@ bool TargetInstrInfo::getInsertSubregInputs(
// Returns a MIRPrinter comment for this machine operand.
std::string TargetInstrInfo::createMIROperandComment(
const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
- const TargetRegisterInfo *TRI) const {
+ const TargetRegisterInfo * /*RemoveMe*/) const {
if (!MI.isInlineAsm())
return "";
@@ -2081,12 +2071,8 @@ std::string TargetInstrInfo::createMIROperandComment(
OS << F.getKindName();
unsigned RCID;
- if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) {
- if (TRI) {
- OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
- } else
- OS << ":RC" << RCID;
- }
+ if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID))
+ OS << ':' << TRI.getRegClassName(TRI.getRegClass(RCID));
if (F.isMemKind()) {
InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 9a7512b77ecdb..19f421a4a081b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -91,7 +91,7 @@ static cl::opt<unsigned> GatherOptSearchLimit(
"machine-combiner gather pattern optimization"));
AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
- : AArch64GenInstrInfo(STI, AArch64::ADJCALLSTACKDOWN,
+ : AArch64GenInstrInfo(STI, RI, AArch64::ADJCALLSTACKDOWN,
AArch64::ADJCALLSTACKUP, AArch64::CATCHRET),
RI(STI.getTargetTriple(), STI.getHwMode()), Subtarget(STI) {}
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index 3e256cce97afb..01040854e1577 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -29,7 +29,7 @@ using namespace llvm;
#include "R600GenInstrInfo.inc"
R600InstrInfo::R600InstrInfo(const R600Subtarget &ST)
- : R600GenInstrInfo(ST, -1, -1), RI(), ST(ST) {}
+ : R600GenInstrInfo(ST, RI, -1, -1), RI(), ST(ST) {}
bool R600InstrInfo::isVector(const MachineInstr &MI) const {
return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f06c06dd203b3..1b855248bb1fd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -62,7 +62,8 @@ static cl::opt<bool> Fix16BitCopies(
cl::ReallyHidden);
SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
- : AMDGPUGenInstrInfo(ST, AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
+ : AMDGPUGenInstrInfo(ST, RI, AMDGPU::ADJCALLSTACKUP,
+ AMDGPU::ADJCALLSTACKDOWN),
RI(ST), ST(ST) {
SchedModel.init(&ST);
}
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 05bcb3596ac48..2dec6ffd89a75 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -44,7 +44,8 @@ enum TSFlagsConstants {
void ARCInstrInfo::anchor() {}
ARCInstrInfo::ARCInstrInfo(const ARCSubtarget &ST)
- : ARCGenInstrInfo(ST, ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI(ST) {}
+ : ARCGenInstrInfo(ST, RI, ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP),
+ RI(ST) {}
static bool isZeroImm(const MachineOperand &Op) {
return Op.isImm() && Op.getImm() == 0;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 5c35b3327c16d..b5280812e8b37 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -107,8 +107,9 @@ static const ARM_MLxEntry ARM_MLxTable[] = {
{ ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
};
-ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
- : ARMGenInstrInfo(STI, ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
+ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI,
+ const ARMBaseRegisterInfo &TRI)
+ : ARMGenInstrInfo(STI, TRI, ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
Subtarget(STI) {
for (unsigned i = 0, e = std::size(ARM_MLxTable); i != e; ++i) {
if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 71de3c6ad597a..213333b23ea92 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -44,7 +44,8 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
protected:
// Can be only subclassed.
- explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
+ explicit ARMBaseInstrInfo(const ARMSubtarget &STI,
+ const ARMBaseRegisterInfo &TRI);
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
unsigned LoadImmOpc, unsigned LoadOpc) const;
@@ -125,7 +126,11 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
// if there is not such an opcode.
virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
- virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
+ const ARMBaseRegisterInfo &getRegisterInfo() const {
+ return static_cast<const ARMBaseRegisterInfo &>(
+ TargetInstrInfo::getRegisterInfo());
+ }
+
const ARMSubtarget &getSubtarget() const { return Subtarget; }
ScheduleHazardRecognizer *
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index c684de7252e5d..f37054736b730 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -25,7 +25,8 @@
#include "llvm/MC/MCInst.h"
using namespace llvm;
-ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) : ARMBaseInstrInfo(STI) {}
+ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
+ : ARMBaseInstrInfo(STI, RI) {}
/// Return the noop instruction to use for a noop.
MCInst ARMInstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.h b/llvm/lib/Target/ARM/ARMInstrInfo.h
index 178d7a2c630e4..9feaf1440f2b2 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.h
@@ -35,7 +35,7 @@ class ARMInstrInfo : public ARMBaseInstrInfo {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- const ARMRegisterInfo &getRegisterInfo() const override { return RI; }
+ const ARMRegisterInfo &getRegisterInfo() const { return RI; }
private:
void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index 4b8c2fd569ead..f95ba6a4d86fb 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -24,7 +24,7 @@
using namespace llvm;
Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
- : ARMBaseInstrInfo(STI), RI(STI) {}
+ : ARMBaseInstrInfo(STI, RI), RI(STI) {}
/// Return the noop instruction to use for a noop.
MCInst Thumb1InstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.h b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
index 68b326c0ebef6..16350a65a6198 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
@@ -35,7 +35,7 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
+ const ThumbRegisterInfo &getRegisterInfo() const { return RI; }
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, Register DestReg, Register SrcReg,
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 431ce38ad6e99..9e924e61a5ba5 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -46,7 +46,7 @@ PreferNoCSEL("prefer-no-csel", cl::Hidden,
cl::init(false));
Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
- : ARMBaseInstrInfo(STI), RI(STI) {}
+ : ARMBaseInstrInfo(STI, RI), RI(STI) {}
/// Return the noop instruction to use for a noop.
MCInst Thumb2InstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.h b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
index 3ec3a6216b9f6..3e97fc550cbf9 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
@@ -58,7 +58,7 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
+ const ThumbRegisterInfo &getRegisterInfo() const { return RI; }
MachineInstr *optimizeSelect(MachineInstr &MI,
SmallPtrSetImpl<MachineInstr *> &SeenMIs,
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
index ce9908597dcac..5e247cb64a991 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
@@ -30,8 +30,8 @@
namespace llvm {
AVRInstrInfo::AVRInstrInfo(const AVRSubtarget &STI)
- : AVRGenInstrInfo(STI, AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI(),
- STI(STI) {}
+ : AVRGenInstrInfo(STI, RI, AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP),
+ RI(), STI(STI) {}
void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInst...
[truncated]
|
Member
|
@llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesBoth conceptually belong to the same subtarget, so it should not Most targets placed their TargetRegisterInfo as a member Patch is 45.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/158224.diff 50 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 6a624a7052cdd..802cca6022074 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -113,9 +113,12 @@ struct ExtAddrMode {
///
class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
protected:
- TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
- unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
- : CallFrameSetupOpcode(CFSetupOpcode),
+ const TargetRegisterInfo &TRI;
+
+ TargetInstrInfo(const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u,
+ unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u,
+ unsigned ReturnOpcode = ~0u)
+ : TRI(TRI), CallFrameSetupOpcode(CFSetupOpcode),
CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
ReturnOpcode(ReturnOpcode) {}
@@ -124,6 +127,8 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
virtual ~TargetInstrInfo();
+ const TargetRegisterInfo &getRegisterInfo() const { return TRI; }
+
static bool isGenericOpcode(unsigned Opc) {
return Opc <= TargetOpcode::GENERIC_OP_END;
}
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index b0009560d3fcb..e186932d88309 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -60,20 +60,20 @@ TargetInstrInfo::~TargetInstrInfo() = default;
const TargetRegisterClass *
TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
- const TargetRegisterInfo *TRI) const {
+ const TargetRegisterInfo * /*RemoveMe*/) const {
if (OpNum >= MCID.getNumOperands())
return nullptr;
short RegClass = MCID.operands()[OpNum].RegClass;
if (MCID.operands()[OpNum].isLookupPtrRegClass())
- return TRI->getPointerRegClass(RegClass);
+ return TRI.getPointerRegClass(RegClass);
// Instructions like INSERT_SUBREG do not have fixed register classes.
if (RegClass < 0)
return nullptr;
// Otherwise just look it up normally.
- return TRI->getRegClass(RegClass);
+ return TRI.getRegClass(RegClass);
}
/// insertNoop - Insert a noop into the instruction stream at the specified
@@ -220,13 +220,11 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
// %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
SmallVector<unsigned> UpdateImplicitDefIdx;
if (HasDef && MI.hasImplicitDef()) {
- const TargetRegisterInfo *TRI =
- MI.getMF()->getSubtarget().getRegisterInfo();
for (auto [OpNo, MO] : llvm::enumerate(MI.implicit_operands())) {
Register ImplReg = MO.getReg();
if ((ImplReg.isVirtual() && ImplReg == Reg0) ||
(ImplReg.isPhysical() && Reg0.isPhysical() &&
- TRI->isSubRegisterEq(ImplReg, Reg0)))
+ TRI.isSubRegisterEq(ImplReg, Reg0)))
UpdateImplicitDefIdx.push_back(OpNo + MI.getNumExplicitOperands());
}
}
@@ -422,37 +420,35 @@ bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
unsigned SubIdx, unsigned &Size,
unsigned &Offset,
const MachineFunction &MF) const {
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (!SubIdx) {
- Size = TRI->getSpillSize(*RC);
+ Size = TRI.getSpillSize(*RC);
Offset = 0;
return true;
}
- unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
+ unsigned BitSize = TRI.getSubRegIdxSize(SubIdx);
// Convert bit size to byte size.
if (BitSize % 8)
return false;
- int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
+ int BitOffset = TRI.getSubRegIdxOffset(SubIdx);
if (BitOffset < 0 || BitOffset % 8)
return false;
Size = BitSize / 8;
Offset = (unsigned)BitOffset / 8;
- assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
+ assert(TRI.getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
if (!MF.getDataLayout().isLittleEndian()) {
- Offset = TRI->getSpillSize(*RC) - (Offset + Size);
+ Offset = TRI.getSpillSize(*RC) - (Offset + Size);
}
return true;
}
-void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- Register DestReg, unsigned SubIdx,
- const MachineInstr &Orig,
- const TargetRegisterInfo &TRI) const {
+void TargetInstrInfo::reMaterialize(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
+ unsigned SubIdx, const MachineInstr &Orig,
+ const TargetRegisterInfo & /*Remove me*/) const {
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
MBB.insert(I, MI);
@@ -723,7 +719,6 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
// actual load size is.
int64_t MemSize = 0;
const MachineFrameInfo &MFI = MF.getFrameInfo();
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (Flags & MachineMemOperand::MOStore) {
MemSize = MFI.getObjectSize(FI);
@@ -732,7 +727,7 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
int64_t OpSize = MFI.getObjectSize(FI);
if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {
- unsigned SubRegSize = TRI->getSubRegIdxSize(SubReg);
+ unsigned SubRegSize = TRI.getSubRegIdxSize(SubReg);
if (SubRegSize > 0 && !(SubRegSize % 8))
OpSize = SubRegSize / 8;
}
@@ -797,11 +792,11 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
// code.
BuildMI(*MBB, Pos, MI.getDebugLoc(), get(TargetOpcode::KILL)).add(MO);
} else {
- storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI,
+ storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, &TRI,
Register());
}
} else
- loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI, Register());
+ loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, &TRI, Register());
return &*--Pos;
}
@@ -877,8 +872,8 @@ static void transferImplicitOperands(MachineInstr *MI,
}
}
-void TargetInstrInfo::lowerCopy(MachineInstr *MI,
- const TargetRegisterInfo *TRI) const {
+void TargetInstrInfo::lowerCopy(
+ MachineInstr *MI, const TargetRegisterInfo * /*Remove me*/) const {
if (MI->allDefsAreDead()) {
MI->setDesc(get(TargetOpcode::KILL));
return;
@@ -908,7 +903,7 @@ void TargetInstrInfo::lowerCopy(MachineInstr *MI,
SrcMO.getReg().isPhysical() ? SrcMO.isRenamable() : false);
if (MI->getNumOperands() > 2)
- transferImplicitOperands(MI, TRI);
+ transferImplicitOperands(MI, &TRI);
MI->eraseFromParent();
}
@@ -1324,8 +1319,7 @@ void TargetInstrInfo::reassociateOps(
MachineFunction *MF = Root.getMF();
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
- const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
- const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
+ const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, &TRI);
MachineOperand &OpA = Prev.getOperand(OperandIndices[1]);
MachineOperand &OpB = Root.getOperand(OperandIndices[2]);
@@ -1707,8 +1701,7 @@ bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
// stack slot reference to depend on the instruction that does the
// modification.
const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
+ return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), &TRI);
}
// Provide a global flag for disabling the PreRA hazard recognizer that targets
@@ -1741,11 +1734,11 @@ CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
// Default implementation of getMemOperandWithOffset.
bool TargetInstrInfo::getMemOperandWithOffset(
const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset,
- bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const {
+ bool &OffsetIsScalable, const TargetRegisterInfo * /*RemoveMe*/) const {
SmallVector<const MachineOperand *, 4> BaseOps;
LocationSize Width = LocationSize::precise(0);
if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable,
- Width, TRI) ||
+ Width, &TRI) ||
BaseOps.size() != 1)
return false;
BaseOp = BaseOps.front();
@@ -1866,7 +1859,6 @@ std::optional<ParamLoadedValue>
TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
Register Reg) const {
const MachineFunction *MF = MI.getMF();
- const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
DIExpression *Expr = DIExpression::get(MF->getFunction().getContext(), {});
int64_t Offset;
bool OffsetIsScalable;
@@ -1897,7 +1889,6 @@ TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
// Only describe memory which provably does not escape the function. As
// described in llvm.org/PR43343, escaped memory may be clobbered by the
// callee (or by another thread).
- const auto &TII = MF->getSubtarget().getInstrInfo();
const MachineFrameInfo &MFI = MF->getFrameInfo();
const MachineMemOperand *MMO = MI.memoperands()[0];
const PseudoSourceValue *PSV = MMO->getPseudoValue();
@@ -1908,8 +1899,7 @@ TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
return std::nullopt;
const MachineOperand *BaseOp;
- if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
- TRI))
+ if (!getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, &TRI))
return std::nullopt;
// FIXME: Scalable offsets are not yet handled in the offset code below.
@@ -2048,7 +2038,7 @@ bool TargetInstrInfo::getInsertSubregInputs(
// Returns a MIRPrinter comment for this machine operand.
std::string TargetInstrInfo::createMIROperandComment(
const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
- const TargetRegisterInfo *TRI) const {
+ const TargetRegisterInfo * /*RemoveMe*/) const {
if (!MI.isInlineAsm())
return "";
@@ -2081,12 +2071,8 @@ std::string TargetInstrInfo::createMIROperandComment(
OS << F.getKindName();
unsigned RCID;
- if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) {
- if (TRI) {
- OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
- } else
- OS << ":RC" << RCID;
- }
+ if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID))
+ OS << ':' << TRI.getRegClassName(TRI.getRegClass(RCID));
if (F.isMemKind()) {
InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 9a7512b77ecdb..19f421a4a081b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -91,7 +91,7 @@ static cl::opt<unsigned> GatherOptSearchLimit(
"machine-combiner gather pattern optimization"));
AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
- : AArch64GenInstrInfo(STI, AArch64::ADJCALLSTACKDOWN,
+ : AArch64GenInstrInfo(STI, RI, AArch64::ADJCALLSTACKDOWN,
AArch64::ADJCALLSTACKUP, AArch64::CATCHRET),
RI(STI.getTargetTriple(), STI.getHwMode()), Subtarget(STI) {}
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index 3e256cce97afb..01040854e1577 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -29,7 +29,7 @@ using namespace llvm;
#include "R600GenInstrInfo.inc"
R600InstrInfo::R600InstrInfo(const R600Subtarget &ST)
- : R600GenInstrInfo(ST, -1, -1), RI(), ST(ST) {}
+ : R600GenInstrInfo(ST, RI, -1, -1), RI(), ST(ST) {}
bool R600InstrInfo::isVector(const MachineInstr &MI) const {
return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f06c06dd203b3..1b855248bb1fd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -62,7 +62,8 @@ static cl::opt<bool> Fix16BitCopies(
cl::ReallyHidden);
SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
- : AMDGPUGenInstrInfo(ST, AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
+ : AMDGPUGenInstrInfo(ST, RI, AMDGPU::ADJCALLSTACKUP,
+ AMDGPU::ADJCALLSTACKDOWN),
RI(ST), ST(ST) {
SchedModel.init(&ST);
}
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 05bcb3596ac48..2dec6ffd89a75 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -44,7 +44,8 @@ enum TSFlagsConstants {
void ARCInstrInfo::anchor() {}
ARCInstrInfo::ARCInstrInfo(const ARCSubtarget &ST)
- : ARCGenInstrInfo(ST, ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI(ST) {}
+ : ARCGenInstrInfo(ST, RI, ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP),
+ RI(ST) {}
static bool isZeroImm(const MachineOperand &Op) {
return Op.isImm() && Op.getImm() == 0;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 5c35b3327c16d..b5280812e8b37 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -107,8 +107,9 @@ static const ARM_MLxEntry ARM_MLxTable[] = {
{ ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
};
-ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
- : ARMGenInstrInfo(STI, ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
+ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI,
+ const ARMBaseRegisterInfo &TRI)
+ : ARMGenInstrInfo(STI, TRI, ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
Subtarget(STI) {
for (unsigned i = 0, e = std::size(ARM_MLxTable); i != e; ++i) {
if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 71de3c6ad597a..213333b23ea92 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -44,7 +44,8 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
protected:
// Can be only subclassed.
- explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
+ explicit ARMBaseInstrInfo(const ARMSubtarget &STI,
+ const ARMBaseRegisterInfo &TRI);
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
unsigned LoadImmOpc, unsigned LoadOpc) const;
@@ -125,7 +126,11 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
// if there is not such an opcode.
virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
- virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
+ const ARMBaseRegisterInfo &getRegisterInfo() const {
+ return static_cast<const ARMBaseRegisterInfo &>(
+ TargetInstrInfo::getRegisterInfo());
+ }
+
const ARMSubtarget &getSubtarget() const { return Subtarget; }
ScheduleHazardRecognizer *
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index c684de7252e5d..f37054736b730 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -25,7 +25,8 @@
#include "llvm/MC/MCInst.h"
using namespace llvm;
-ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) : ARMBaseInstrInfo(STI) {}
+ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
+ : ARMBaseInstrInfo(STI, RI) {}
/// Return the noop instruction to use for a noop.
MCInst ARMInstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.h b/llvm/lib/Target/ARM/ARMInstrInfo.h
index 178d7a2c630e4..9feaf1440f2b2 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.h
@@ -35,7 +35,7 @@ class ARMInstrInfo : public ARMBaseInstrInfo {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- const ARMRegisterInfo &getRegisterInfo() const override { return RI; }
+ const ARMRegisterInfo &getRegisterInfo() const { return RI; }
private:
void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index 4b8c2fd569ead..f95ba6a4d86fb 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -24,7 +24,7 @@
using namespace llvm;
Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
- : ARMBaseInstrInfo(STI), RI(STI) {}
+ : ARMBaseInstrInfo(STI, RI), RI(STI) {}
/// Return the noop instruction to use for a noop.
MCInst Thumb1InstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.h b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
index 68b326c0ebef6..16350a65a6198 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
@@ -35,7 +35,7 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
+ const ThumbRegisterInfo &getRegisterInfo() const { return RI; }
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, Register DestReg, Register SrcReg,
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 431ce38ad6e99..9e924e61a5ba5 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -46,7 +46,7 @@ PreferNoCSEL("prefer-no-csel", cl::Hidden,
cl::init(false));
Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
- : ARMBaseInstrInfo(STI), RI(STI) {}
+ : ARMBaseInstrInfo(STI, RI), RI(STI) {}
/// Return the noop instruction to use for a noop.
MCInst Thumb2InstrInfo::getNop() const {
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.h b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
index 3ec3a6216b9f6..3e97fc550cbf9 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
@@ -58,7 +58,7 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
+ const ThumbRegisterInfo &getRegisterInfo() const { return RI; }
MachineInstr *optimizeSelect(MachineInstr &MI,
SmallPtrSetImpl<MachineInstr *> &SeenMIs,
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
index ce9908597dcac..5e247cb64a991 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
@@ -30,8 +30,8 @@
namespace llvm {
AVRInstrInfo::AVRInstrInfo(const AVRSubtarget &STI)
- : AVRGenInstrInfo(STI, AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI(),
- STI(STI) {}
+ : AVRGenInstrInfo(STI, RI, AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP),
+ RI(), STI(STI) {}
void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInst...
[truncated]
|
This was referenced Sep 12, 2025
| : CallFrameSetupOpcode(CFSetupOpcode), | ||
| const TargetRegisterInfo &TRI; | ||
|
|
||
| TargetInstrInfo(const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, |
Contributor
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Or should the argument be TargetSubtargetInfo?
| << " explicit " << ClassName | ||
| << "(const TargetSubtargetInfo &STI, unsigned CFSetupOpcode = ~0u, " | ||
| "unsigned CFDestroyOpcode = ~0u, " | ||
| << "(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, " |
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Can we get TRI from STI? Or is it because some targets have TRI inside TII?
Contributor
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No. Most targets have TRI inside TII. After this PR, they all do. Later we should probably remove the query for TRI from STI.
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Most targets have TRI inside TII. After this PR, they all do.
I'd prefer the opposite.
I think most traget have TRI inside TII because it was easier to call this->getRegInfo() from inside a TII method than to call MI->getMF().getSubtarget()->getRegInfo(). If we have an STI reference as a member of TII, we could get TRI by this->STI.getRegInfo().
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IMO TRI is an arbitrary distinction from TII, and might as well be part of it.
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It is because many TII and TRI methods (especially those that have MF as an argument) are misplaced. They should've been members of STI, FrameLowering, or a separate class.
There is a clear distinction when it comes to low-level queries like hasRegUnit or hasSideEffects (but not e.g., getReservedRegs that is ABI-dependent).
Not a very strong objection, but I think having TRI inside STI would make more sense and reduce the number of arguments to TII constructors.
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Thas sounds reasonable, but in this case (and in the one I suggested above as I just realized) TRI calls won't be devirtualized, right?
I guess I can be convinced if TRI virtual calls lead to compile time regressions.
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I was trying to make it so targets would be forced to use the local reference in their own code but dropped that somewhere in the middle. I could revisit to make TRI private and force access through something that performs the local target cast
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IIUC If the local reference/instance is of the derived type, cast is unnecessary? I would hate it if we have to getRegisterInfo<MyRegisterInfo>() in every place we need to access TRI from inside TII methods.
Or did you mean something else?
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If TRI is just a member in TargetInstrInfo, the derived TargetInstrInfo class uses don't obviously know that TRI is the appropriate target one
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I was trying to make it so targets would be forced to use the local reference in their own code
I read it as "targets have their own copy of the reference in derived classes".
I would hate it if we have to
getRegisterInfo<MyRegisterInfo>()in every place we need to access TRI from inside TII methods.
On second thought, it might not be that bad. We already have getSubtarget<MySubtarget>(), and those who don't like verbosity can have a typed reference in derived class.
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please can you merge with trunk latest
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LGTM as long as @s-barannikov is now OK with the approach
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It seems I can still store TRI in STI and pass it to TII constructor, so no objections.
Both conceptually belong to the same subtarget, so it should not be necessary to pass in the context TargetRegisterInfo to any TargetInstrInfo member. Add this reference so those superfluous arguments can be removed. Most targets placed their TargetRegisterInfo as a member in TargetInstrInfo. A few had this owned by the TargetSubtargetInfo, so unify all targets to look the same.
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Both conceptually belong to the same subtarget, so it should not
be necessary to pass in the context TargetRegisterInfo to any
TargetInstrInfo member. Add this reference so those superfluous
arguments can be removed.
Most targets placed their TargetRegisterInfo as a member
in TargetInstrInfo. A few had this owned by the TargetSubtargetInfo,
so unify all targets to look the same.