Skip to content

Commit b9ea93c

Browse files
authored
[InstCombine] Fold operation into select, when one operand is zext of select's condition (#166816)
Proof https://alive2.llvm.org/ce/z/oCQyTG
1 parent 21c1b78 commit b9ea93c

File tree

2 files changed

+9
-23
lines changed

2 files changed

+9
-23
lines changed

llvm/lib/Transforms/InstCombine/InstructionCombining.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1758,6 +1758,9 @@ static Value *simplifyOperationIntoSelectOperand(Instruction &I, SelectInst *SI,
17581758
m_Specific(Op), m_Value(V))) &&
17591759
isGuaranteedNotToBeUndefOrPoison(V)) {
17601760
// Pass
1761+
} else if (match(Op, m_ZExt(m_Specific(SI->getCondition())))) {
1762+
V = IsTrueArm ? ConstantInt::get(Op->getType(), 1)
1763+
: ConstantInt::getNullValue(Op->getType());
17611764
} else {
17621765
V = Op;
17631766
}

llvm/test/Transforms/InstCombine/binop-select.ll

Lines changed: 6 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -406,10 +406,7 @@ define i32 @ashr_sel_op1_use(i1 %b) {
406406

407407
define i8 @commonArgWithOr0(i1 %arg0) {
408408
; CHECK-LABEL: @commonArgWithOr0(
409-
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
410-
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 0, i8 8
411-
; CHECK-NEXT: [[V2:%.*]] = or disjoint i8 [[V1]], [[V0]]
412-
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
409+
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 17, i8 24
413410
; CHECK-NEXT: ret i8 [[V3]]
414411
;
415412
%v0 = zext i1 %arg0 to i8
@@ -433,10 +430,7 @@ define i8 @commonArgWithOr1(i1 %arg0) {
433430

434431
define i8 @commonArgWithOr2(i1 %arg0) {
435432
; CHECK-LABEL: @commonArgWithOr2(
436-
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
437-
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 5, i8 42
438-
; CHECK-NEXT: [[V2:%.*]] = or i8 [[V1]], [[V0]]
439-
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
433+
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 21, i8 58
440434
; CHECK-NEXT: ret i8 [[V3]]
441435
;
442436
%v0 = zext i1 %arg0 to i8
@@ -496,10 +490,7 @@ define i8 @commonArgWithAnd3(i1 %arg0) {
496490

497491
define i8 @commonArgWithXor0(i1 %arg0) {
498492
; CHECK-LABEL: @commonArgWithXor0(
499-
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
500-
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 0, i8 8
501-
; CHECK-NEXT: [[V2:%.*]] = or disjoint i8 [[V1]], [[V0]]
502-
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
493+
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 17, i8 24
503494
; CHECK-NEXT: ret i8 [[V3]]
504495
;
505496
%v0 = zext i1 %arg0 to i8
@@ -511,9 +502,7 @@ define i8 @commonArgWithXor0(i1 %arg0) {
511502

512503
define i8 @commonArgWithXor1(i1 %arg0) {
513504
; CHECK-LABEL: @commonArgWithXor1(
514-
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
515-
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 9, i8 1
516-
; CHECK-NEXT: [[V2:%.*]] = xor i8 [[V1]], [[V0]]
505+
; CHECK-NEXT: [[V2:%.*]] = select i1 [[ARG0:%.*]], i8 8, i8 1
517506
; CHECK-NEXT: ret i8 [[V2]]
518507
;
519508
%v0 = zext i1 %arg0 to i8
@@ -524,10 +513,7 @@ define i8 @commonArgWithXor1(i1 %arg0) {
524513

525514
define i8 @commonArgWithXor2(i1 %arg0) {
526515
; CHECK-LABEL: @commonArgWithXor2(
527-
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
528-
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 1, i8 7
529-
; CHECK-NEXT: [[V2:%.*]] = xor i8 [[V1]], [[V0]]
530-
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
516+
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 16, i8 23
531517
; CHECK-NEXT: ret i8 [[V3]]
532518
;
533519
%v0 = zext i1 %arg0 to i8
@@ -539,10 +525,7 @@ define i8 @commonArgWithXor2(i1 %arg0) {
539525

540526
define i8 @commonArgWithXor3(i1 %arg0) {
541527
; CHECK-LABEL: @commonArgWithXor3(
542-
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
543-
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 5, i8 45
544-
; CHECK-NEXT: [[V2:%.*]] = xor i8 [[V1]], [[V0]]
545-
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
528+
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 20, i8 61
546529
; CHECK-NEXT: ret i8 [[V3]]
547530
;
548531
%v0 = zext i1 %arg0 to i8

0 commit comments

Comments
 (0)