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RKSimonRKSimon
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[X86][BtVer2] SSE2 vector shifts has local forwarding disabled
Similar to horizontal ops on D56777, the sse2 (but not mmx) bit shift ops has local forwarding disabled, adding +1cy to the use latency for the result. Differential Revision: https://reviews.llvm.org/D57026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351817 91177308-0d34-0410-b5e6-96231b3b80d8
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4 files changed

+98
-98
lines changed

4 files changed

+98
-98
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‎lib/Target/X86/X86ScheduleBtVer2.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -487,11 +487,11 @@ defm : JWriteResFpuPair<WriteVecALUX, [JFPU01, JVALU], 1>;
487487
defm : X86WriteResPairUnsupported<WriteVecALUY>;
488488
defm : X86WriteResPairUnsupported<WriteVecALUZ>;
489489
defm : JWriteResFpuPair<WriteVecShift, [JFPU01, JVALU], 1>;
490-
defm : JWriteResFpuPair<WriteVecShiftX, [JFPU01, JVALU], 1>;
490+
defm : JWriteResFpuPair<WriteVecShiftX, [JFPU01, JVALU], 2>; // +1cy latency.
491491
defm : X86WriteResPairUnsupported<WriteVecShiftY>;
492492
defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
493493
defm : JWriteResFpuPair<WriteVecShiftImm, [JFPU01, JVALU], 1>;
494-
defm : JWriteResFpuPair<WriteVecShiftImmX,[JFPU01, JVALU], 1>;
494+
defm : JWriteResFpuPair<WriteVecShiftImmX,[JFPU01, JVALU], 2>; // +1cy latency.
495495
defm : X86WriteResPairUnsupported<WriteVecShiftImmY>;
496496
defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
497497
defm : X86WriteResPairUnsupported<WriteVarVecShift>;

‎test/CodeGen/X86/sse2-schedule.ll‎

Lines changed: 48 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -12146,16 +12146,16 @@ define <4 x i32> @test_pslld(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
1214612146
;
1214712147
; BTVER2-SSE-LABEL: test_pslld:
1214812148
; BTVER2-SSE: # %bb.0:
12149-
; BTVER2-SSE-NEXT: pslld %xmm1, %xmm0 # sched: [1:0.50]
12150-
; BTVER2-SSE-NEXT: pslld (%rdi), %xmm0 # sched: [6:1.00]
12151-
; BTVER2-SSE-NEXT: pslld $2, %xmm0 # sched: [1:0.50]
12149+
; BTVER2-SSE-NEXT: pslld %xmm1, %xmm0 # sched: [2:0.50]
12150+
; BTVER2-SSE-NEXT: pslld (%rdi), %xmm0 # sched: [7:1.00]
12151+
; BTVER2-SSE-NEXT: pslld $2, %xmm0 # sched: [2:0.50]
1215212152
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
1215312153
;
1215412154
; BTVER2-LABEL: test_pslld:
1215512155
; BTVER2: # %bb.0:
12156-
; BTVER2-NEXT: vpslld %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
12157-
; BTVER2-NEXT: vpslld (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
12158-
; BTVER2-NEXT: vpslld $2, %xmm0, %xmm0 # sched: [1:0.50]
12156+
; BTVER2-NEXT: vpslld %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
12157+
; BTVER2-NEXT: vpslld (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
12158+
; BTVER2-NEXT: vpslld $2, %xmm0, %xmm0 # sched: [2:0.50]
1215912159
; BTVER2-NEXT: retq # sched: [4:1.00]
1216012160
;
1216112161
; ZNVER1-SSE-LABEL: test_pslld:
@@ -12393,16 +12393,16 @@ define <2 x i64> @test_psllq(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
1239312393
;
1239412394
; BTVER2-SSE-LABEL: test_psllq:
1239512395
; BTVER2-SSE: # %bb.0:
12396-
; BTVER2-SSE-NEXT: psllq %xmm1, %xmm0 # sched: [1:0.50]
12397-
; BTVER2-SSE-NEXT: psllq (%rdi), %xmm0 # sched: [6:1.00]
12398-
; BTVER2-SSE-NEXT: psllq $2, %xmm0 # sched: [1:0.50]
12396+
; BTVER2-SSE-NEXT: psllq %xmm1, %xmm0 # sched: [2:0.50]
12397+
; BTVER2-SSE-NEXT: psllq (%rdi), %xmm0 # sched: [7:1.00]
12398+
; BTVER2-SSE-NEXT: psllq $2, %xmm0 # sched: [2:0.50]
1239912399
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
1240012400
;
1240112401
; BTVER2-LABEL: test_psllq:
1240212402
; BTVER2: # %bb.0:
12403-
; BTVER2-NEXT: vpsllq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
12404-
; BTVER2-NEXT: vpsllq (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
12405-
; BTVER2-NEXT: vpsllq $2, %xmm0, %xmm0 # sched: [1:0.50]
12403+
; BTVER2-NEXT: vpsllq %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
12404+
; BTVER2-NEXT: vpsllq (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
12405+
; BTVER2-NEXT: vpsllq $2, %xmm0, %xmm0 # sched: [2:0.50]
1240612406
; BTVER2-NEXT: retq # sched: [4:1.00]
1240712407
;
1240812408
; ZNVER1-SSE-LABEL: test_psllq:
@@ -12535,16 +12535,16 @@ define <8 x i16> @test_psllw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
1253512535
;
1253612536
; BTVER2-SSE-LABEL: test_psllw:
1253712537
; BTVER2-SSE: # %bb.0:
12538-
; BTVER2-SSE-NEXT: psllw %xmm1, %xmm0 # sched: [1:0.50]
12539-
; BTVER2-SSE-NEXT: psllw (%rdi), %xmm0 # sched: [6:1.00]
12540-
; BTVER2-SSE-NEXT: psllw $2, %xmm0 # sched: [1:0.50]
12538+
; BTVER2-SSE-NEXT: psllw %xmm1, %xmm0 # sched: [2:0.50]
12539+
; BTVER2-SSE-NEXT: psllw (%rdi), %xmm0 # sched: [7:1.00]
12540+
; BTVER2-SSE-NEXT: psllw $2, %xmm0 # sched: [2:0.50]
1254112541
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
1254212542
;
1254312543
; BTVER2-LABEL: test_psllw:
1254412544
; BTVER2: # %bb.0:
12545-
; BTVER2-NEXT: vpsllw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
12546-
; BTVER2-NEXT: vpsllw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
12547-
; BTVER2-NEXT: vpsllw $2, %xmm0, %xmm0 # sched: [1:0.50]
12545+
; BTVER2-NEXT: vpsllw %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
12546+
; BTVER2-NEXT: vpsllw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
12547+
; BTVER2-NEXT: vpsllw $2, %xmm0, %xmm0 # sched: [2:0.50]
1254812548
; BTVER2-NEXT: retq # sched: [4:1.00]
1254912549
;
1255012550
; ZNVER1-SSE-LABEL: test_psllw:
@@ -12677,16 +12677,16 @@ define <4 x i32> @test_psrad(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
1267712677
;
1267812678
; BTVER2-SSE-LABEL: test_psrad:
1267912679
; BTVER2-SSE: # %bb.0:
12680-
; BTVER2-SSE-NEXT: psrad %xmm1, %xmm0 # sched: [1:0.50]
12681-
; BTVER2-SSE-NEXT: psrad (%rdi), %xmm0 # sched: [6:1.00]
12682-
; BTVER2-SSE-NEXT: psrad $2, %xmm0 # sched: [1:0.50]
12680+
; BTVER2-SSE-NEXT: psrad %xmm1, %xmm0 # sched: [2:0.50]
12681+
; BTVER2-SSE-NEXT: psrad (%rdi), %xmm0 # sched: [7:1.00]
12682+
; BTVER2-SSE-NEXT: psrad $2, %xmm0 # sched: [2:0.50]
1268312683
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
1268412684
;
1268512685
; BTVER2-LABEL: test_psrad:
1268612686
; BTVER2: # %bb.0:
12687-
; BTVER2-NEXT: vpsrad %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
12688-
; BTVER2-NEXT: vpsrad (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
12689-
; BTVER2-NEXT: vpsrad $2, %xmm0, %xmm0 # sched: [1:0.50]
12687+
; BTVER2-NEXT: vpsrad %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
12688+
; BTVER2-NEXT: vpsrad (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
12689+
; BTVER2-NEXT: vpsrad $2, %xmm0, %xmm0 # sched: [2:0.50]
1269012690
; BTVER2-NEXT: retq # sched: [4:1.00]
1269112691
;
1269212692
; ZNVER1-SSE-LABEL: test_psrad:
@@ -12819,16 +12819,16 @@ define <8 x i16> @test_psraw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
1281912819
;
1282012820
; BTVER2-SSE-LABEL: test_psraw:
1282112821
; BTVER2-SSE: # %bb.0:
12822-
; BTVER2-SSE-NEXT: psraw %xmm1, %xmm0 # sched: [1:0.50]
12823-
; BTVER2-SSE-NEXT: psraw (%rdi), %xmm0 # sched: [6:1.00]
12824-
; BTVER2-SSE-NEXT: psraw $2, %xmm0 # sched: [1:0.50]
12822+
; BTVER2-SSE-NEXT: psraw %xmm1, %xmm0 # sched: [2:0.50]
12823+
; BTVER2-SSE-NEXT: psraw (%rdi), %xmm0 # sched: [7:1.00]
12824+
; BTVER2-SSE-NEXT: psraw $2, %xmm0 # sched: [2:0.50]
1282512825
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
1282612826
;
1282712827
; BTVER2-LABEL: test_psraw:
1282812828
; BTVER2: # %bb.0:
12829-
; BTVER2-NEXT: vpsraw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
12830-
; BTVER2-NEXT: vpsraw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
12831-
; BTVER2-NEXT: vpsraw $2, %xmm0, %xmm0 # sched: [1:0.50]
12829+
; BTVER2-NEXT: vpsraw %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
12830+
; BTVER2-NEXT: vpsraw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
12831+
; BTVER2-NEXT: vpsraw $2, %xmm0, %xmm0 # sched: [2:0.50]
1283212832
; BTVER2-NEXT: retq # sched: [4:1.00]
1283312833
;
1283412834
; ZNVER1-SSE-LABEL: test_psraw:
@@ -12961,16 +12961,16 @@ define <4 x i32> @test_psrld(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
1296112961
;
1296212962
; BTVER2-SSE-LABEL: test_psrld:
1296312963
; BTVER2-SSE: # %bb.0:
12964-
; BTVER2-SSE-NEXT: psrld %xmm1, %xmm0 # sched: [1:0.50]
12965-
; BTVER2-SSE-NEXT: psrld (%rdi), %xmm0 # sched: [6:1.00]
12966-
; BTVER2-SSE-NEXT: psrld $2, %xmm0 # sched: [1:0.50]
12964+
; BTVER2-SSE-NEXT: psrld %xmm1, %xmm0 # sched: [2:0.50]
12965+
; BTVER2-SSE-NEXT: psrld (%rdi), %xmm0 # sched: [7:1.00]
12966+
; BTVER2-SSE-NEXT: psrld $2, %xmm0 # sched: [2:0.50]
1296712967
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
1296812968
;
1296912969
; BTVER2-LABEL: test_psrld:
1297012970
; BTVER2: # %bb.0:
12971-
; BTVER2-NEXT: vpsrld %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
12972-
; BTVER2-NEXT: vpsrld (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
12973-
; BTVER2-NEXT: vpsrld $2, %xmm0, %xmm0 # sched: [1:0.50]
12971+
; BTVER2-NEXT: vpsrld %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
12972+
; BTVER2-NEXT: vpsrld (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
12973+
; BTVER2-NEXT: vpsrld $2, %xmm0, %xmm0 # sched: [2:0.50]
1297412974
; BTVER2-NEXT: retq # sched: [4:1.00]
1297512975
;
1297612976
; ZNVER1-SSE-LABEL: test_psrld:
@@ -13208,16 +13208,16 @@ define <2 x i64> @test_psrlq(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
1320813208
;
1320913209
; BTVER2-SSE-LABEL: test_psrlq:
1321013210
; BTVER2-SSE: # %bb.0:
13211-
; BTVER2-SSE-NEXT: psrlq %xmm1, %xmm0 # sched: [1:0.50]
13212-
; BTVER2-SSE-NEXT: psrlq (%rdi), %xmm0 # sched: [6:1.00]
13213-
; BTVER2-SSE-NEXT: psrlq $2, %xmm0 # sched: [1:0.50]
13211+
; BTVER2-SSE-NEXT: psrlq %xmm1, %xmm0 # sched: [2:0.50]
13212+
; BTVER2-SSE-NEXT: psrlq (%rdi), %xmm0 # sched: [7:1.00]
13213+
; BTVER2-SSE-NEXT: psrlq $2, %xmm0 # sched: [2:0.50]
1321413214
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
1321513215
;
1321613216
; BTVER2-LABEL: test_psrlq:
1321713217
; BTVER2: # %bb.0:
13218-
; BTVER2-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
13219-
; BTVER2-NEXT: vpsrlq (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
13220-
; BTVER2-NEXT: vpsrlq $2, %xmm0, %xmm0 # sched: [1:0.50]
13218+
; BTVER2-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
13219+
; BTVER2-NEXT: vpsrlq (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
13220+
; BTVER2-NEXT: vpsrlq $2, %xmm0, %xmm0 # sched: [2:0.50]
1322113221
; BTVER2-NEXT: retq # sched: [4:1.00]
1322213222
;
1322313223
; ZNVER1-SSE-LABEL: test_psrlq:
@@ -13350,16 +13350,16 @@ define <8 x i16> @test_psrlw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
1335013350
;
1335113351
; BTVER2-SSE-LABEL: test_psrlw:
1335213352
; BTVER2-SSE: # %bb.0:
13353-
; BTVER2-SSE-NEXT: psrlw %xmm1, %xmm0 # sched: [1:0.50]
13354-
; BTVER2-SSE-NEXT: psrlw (%rdi), %xmm0 # sched: [6:1.00]
13355-
; BTVER2-SSE-NEXT: psrlw $2, %xmm0 # sched: [1:0.50]
13353+
; BTVER2-SSE-NEXT: psrlw %xmm1, %xmm0 # sched: [2:0.50]
13354+
; BTVER2-SSE-NEXT: psrlw (%rdi), %xmm0 # sched: [7:1.00]
13355+
; BTVER2-SSE-NEXT: psrlw $2, %xmm0 # sched: [2:0.50]
1335613356
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
1335713357
;
1335813358
; BTVER2-LABEL: test_psrlw:
1335913359
; BTVER2: # %bb.0:
13360-
; BTVER2-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
13361-
; BTVER2-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
13362-
; BTVER2-NEXT: vpsrlw $2, %xmm0, %xmm0 # sched: [1:0.50]
13360+
; BTVER2-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
13361+
; BTVER2-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
13362+
; BTVER2-NEXT: vpsrlw $2, %xmm0, %xmm0 # sched: [2:0.50]
1336313363
; BTVER2-NEXT: retq # sched: [4:1.00]
1336413364
;
1336513365
; ZNVER1-SSE-LABEL: test_psrlw:

‎test/tools/llvm-mca/X86/BtVer2/resources-avx1.s‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1562,32 +1562,32 @@ vzeroupper
15621562
# CHECK-NEXT: 1 6 1.00 * vpsignd (%rax), %xmm1, %xmm2
15631563
# CHECK-NEXT: 1 1 0.50 vpsignw %xmm0, %xmm1, %xmm2
15641564
# CHECK-NEXT: 1 6 1.00 * vpsignw (%rax), %xmm1, %xmm2
1565-
# CHECK-NEXT: 1 1 0.50 vpslld $1, %xmm0, %xmm2
1566-
# CHECK-NEXT: 1 1 0.50 vpslld %xmm0, %xmm1, %xmm2
1567-
# CHECK-NEXT: 1 6 1.00 * vpslld (%rax), %xmm1, %xmm2
1565+
# CHECK-NEXT: 1 2 0.50 vpslld $1, %xmm0, %xmm2
1566+
# CHECK-NEXT: 1 2 0.50 vpslld %xmm0, %xmm1, %xmm2
1567+
# CHECK-NEXT: 1 7 1.00 * vpslld (%rax), %xmm1, %xmm2
15681568
# CHECK-NEXT: 1 1 0.50 vpslldq $1, %xmm1, %xmm2
1569-
# CHECK-NEXT: 1 1 0.50 vpsllq $1, %xmm0, %xmm2
1570-
# CHECK-NEXT: 1 1 0.50 vpsllq %xmm0, %xmm1, %xmm2
1571-
# CHECK-NEXT: 1 6 1.00 * vpsllq (%rax), %xmm1, %xmm2
1572-
# CHECK-NEXT: 1 1 0.50 vpsllw $1, %xmm0, %xmm2
1573-
# CHECK-NEXT: 1 1 0.50 vpsllw %xmm0, %xmm1, %xmm2
1574-
# CHECK-NEXT: 1 6 1.00 * vpsllw (%rax), %xmm1, %xmm2
1575-
# CHECK-NEXT: 1 1 0.50 vpsrad $1, %xmm0, %xmm2
1576-
# CHECK-NEXT: 1 1 0.50 vpsrad %xmm0, %xmm1, %xmm2
1577-
# CHECK-NEXT: 1 6 1.00 * vpsrad (%rax), %xmm1, %xmm2
1578-
# CHECK-NEXT: 1 1 0.50 vpsraw $1, %xmm0, %xmm2
1579-
# CHECK-NEXT: 1 1 0.50 vpsraw %xmm0, %xmm1, %xmm2
1580-
# CHECK-NEXT: 1 6 1.00 * vpsraw (%rax), %xmm1, %xmm2
1581-
# CHECK-NEXT: 1 1 0.50 vpsrld $1, %xmm0, %xmm2
1582-
# CHECK-NEXT: 1 1 0.50 vpsrld %xmm0, %xmm1, %xmm2
1583-
# CHECK-NEXT: 1 6 1.00 * vpsrld (%rax), %xmm1, %xmm2
1569+
# CHECK-NEXT: 1 2 0.50 vpsllq $1, %xmm0, %xmm2
1570+
# CHECK-NEXT: 1 2 0.50 vpsllq %xmm0, %xmm1, %xmm2
1571+
# CHECK-NEXT: 1 7 1.00 * vpsllq (%rax), %xmm1, %xmm2
1572+
# CHECK-NEXT: 1 2 0.50 vpsllw $1, %xmm0, %xmm2
1573+
# CHECK-NEXT: 1 2 0.50 vpsllw %xmm0, %xmm1, %xmm2
1574+
# CHECK-NEXT: 1 7 1.00 * vpsllw (%rax), %xmm1, %xmm2
1575+
# CHECK-NEXT: 1 2 0.50 vpsrad $1, %xmm0, %xmm2
1576+
# CHECK-NEXT: 1 2 0.50 vpsrad %xmm0, %xmm1, %xmm2
1577+
# CHECK-NEXT: 1 7 1.00 * vpsrad (%rax), %xmm1, %xmm2
1578+
# CHECK-NEXT: 1 2 0.50 vpsraw $1, %xmm0, %xmm2
1579+
# CHECK-NEXT: 1 2 0.50 vpsraw %xmm0, %xmm1, %xmm2
1580+
# CHECK-NEXT: 1 7 1.00 * vpsraw (%rax), %xmm1, %xmm2
1581+
# CHECK-NEXT: 1 2 0.50 vpsrld $1, %xmm0, %xmm2
1582+
# CHECK-NEXT: 1 2 0.50 vpsrld %xmm0, %xmm1, %xmm2
1583+
# CHECK-NEXT: 1 7 1.00 * vpsrld (%rax), %xmm1, %xmm2
15841584
# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %xmm1, %xmm2
1585-
# CHECK-NEXT: 1 1 0.50 vpsrlq $1, %xmm0, %xmm2
1586-
# CHECK-NEXT: 1 1 0.50 vpsrlq %xmm0, %xmm1, %xmm2
1587-
# CHECK-NEXT: 1 6 1.00 * vpsrlq (%rax), %xmm1, %xmm2
1588-
# CHECK-NEXT: 1 1 0.50 vpsrlw $1, %xmm0, %xmm2
1589-
# CHECK-NEXT: 1 1 0.50 vpsrlw %xmm0, %xmm1, %xmm2
1590-
# CHECK-NEXT: 1 6 1.00 * vpsrlw (%rax), %xmm1, %xmm2
1585+
# CHECK-NEXT: 1 2 0.50 vpsrlq $1, %xmm0, %xmm2
1586+
# CHECK-NEXT: 1 2 0.50 vpsrlq %xmm0, %xmm1, %xmm2
1587+
# CHECK-NEXT: 1 7 1.00 * vpsrlq (%rax), %xmm1, %xmm2
1588+
# CHECK-NEXT: 1 2 0.50 vpsrlw $1, %xmm0, %xmm2
1589+
# CHECK-NEXT: 1 2 0.50 vpsrlw %xmm0, %xmm1, %xmm2
1590+
# CHECK-NEXT: 1 7 1.00 * vpsrlw (%rax), %xmm1, %xmm2
15911591
# CHECK-NEXT: 1 1 0.50 vpsubb %xmm0, %xmm1, %xmm2
15921592
# CHECK-NEXT: 1 6 1.00 * vpsubb (%rax), %xmm1, %xmm2
15931593
# CHECK-NEXT: 1 1 0.50 vpsubd %xmm0, %xmm1, %xmm2

‎test/tools/llvm-mca/X86/BtVer2/resources-sse2.s‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -586,32 +586,32 @@ xorpd (%rax), %xmm2
586586
# CHECK-NEXT: 1 6 1.00 * pshufhw $1, (%rax), %xmm2
587587
# CHECK-NEXT: 1 1 0.50 pshuflw $1, %xmm0, %xmm2
588588
# CHECK-NEXT: 1 6 1.00 * pshuflw $1, (%rax), %xmm2
589-
# CHECK-NEXT: 1 1 0.50 pslld $1, %xmm2
590-
# CHECK-NEXT: 1 1 0.50 pslld %xmm0, %xmm2
591-
# CHECK-NEXT: 1 6 1.00 * pslld (%rax), %xmm2
589+
# CHECK-NEXT: 1 2 0.50 pslld $1, %xmm2
590+
# CHECK-NEXT: 1 2 0.50 pslld %xmm0, %xmm2
591+
# CHECK-NEXT: 1 7 1.00 * pslld (%rax), %xmm2
592592
# CHECK-NEXT: 1 1 0.50 pslldq $1, %xmm2
593-
# CHECK-NEXT: 1 1 0.50 psllq $1, %xmm2
594-
# CHECK-NEXT: 1 1 0.50 psllq %xmm0, %xmm2
595-
# CHECK-NEXT: 1 6 1.00 * psllq (%rax), %xmm2
596-
# CHECK-NEXT: 1 1 0.50 psllw $1, %xmm2
597-
# CHECK-NEXT: 1 1 0.50 psllw %xmm0, %xmm2
598-
# CHECK-NEXT: 1 6 1.00 * psllw (%rax), %xmm2
599-
# CHECK-NEXT: 1 1 0.50 psrad $1, %xmm2
600-
# CHECK-NEXT: 1 1 0.50 psrad %xmm0, %xmm2
601-
# CHECK-NEXT: 1 6 1.00 * psrad (%rax), %xmm2
602-
# CHECK-NEXT: 1 1 0.50 psraw $1, %xmm2
603-
# CHECK-NEXT: 1 1 0.50 psraw %xmm0, %xmm2
604-
# CHECK-NEXT: 1 6 1.00 * psraw (%rax), %xmm2
605-
# CHECK-NEXT: 1 1 0.50 psrld $1, %xmm2
606-
# CHECK-NEXT: 1 1 0.50 psrld %xmm0, %xmm2
607-
# CHECK-NEXT: 1 6 1.00 * psrld (%rax), %xmm2
593+
# CHECK-NEXT: 1 2 0.50 psllq $1, %xmm2
594+
# CHECK-NEXT: 1 2 0.50 psllq %xmm0, %xmm2
595+
# CHECK-NEXT: 1 7 1.00 * psllq (%rax), %xmm2
596+
# CHECK-NEXT: 1 2 0.50 psllw $1, %xmm2
597+
# CHECK-NEXT: 1 2 0.50 psllw %xmm0, %xmm2
598+
# CHECK-NEXT: 1 7 1.00 * psllw (%rax), %xmm2
599+
# CHECK-NEXT: 1 2 0.50 psrad $1, %xmm2
600+
# CHECK-NEXT: 1 2 0.50 psrad %xmm0, %xmm2
601+
# CHECK-NEXT: 1 7 1.00 * psrad (%rax), %xmm2
602+
# CHECK-NEXT: 1 2 0.50 psraw $1, %xmm2
603+
# CHECK-NEXT: 1 2 0.50 psraw %xmm0, %xmm2
604+
# CHECK-NEXT: 1 7 1.00 * psraw (%rax), %xmm2
605+
# CHECK-NEXT: 1 2 0.50 psrld $1, %xmm2
606+
# CHECK-NEXT: 1 2 0.50 psrld %xmm0, %xmm2
607+
# CHECK-NEXT: 1 7 1.00 * psrld (%rax), %xmm2
608608
# CHECK-NEXT: 1 1 0.50 psrldq $1, %xmm2
609-
# CHECK-NEXT: 1 1 0.50 psrlq $1, %xmm2
610-
# CHECK-NEXT: 1 1 0.50 psrlq %xmm0, %xmm2
611-
# CHECK-NEXT: 1 6 1.00 * psrlq (%rax), %xmm2
612-
# CHECK-NEXT: 1 1 0.50 psrlw $1, %xmm2
613-
# CHECK-NEXT: 1 1 0.50 psrlw %xmm0, %xmm2
614-
# CHECK-NEXT: 1 6 1.00 * psrlw (%rax), %xmm2
609+
# CHECK-NEXT: 1 2 0.50 psrlq $1, %xmm2
610+
# CHECK-NEXT: 1 2 0.50 psrlq %xmm0, %xmm2
611+
# CHECK-NEXT: 1 7 1.00 * psrlq (%rax), %xmm2
612+
# CHECK-NEXT: 1 2 0.50 psrlw $1, %xmm2
613+
# CHECK-NEXT: 1 2 0.50 psrlw %xmm0, %xmm2
614+
# CHECK-NEXT: 1 7 1.00 * psrlw (%rax), %xmm2
615615
# CHECK-NEXT: 1 1 0.50 psubb %xmm0, %xmm2
616616
# CHECK-NEXT: 1 6 1.00 * psubb (%rax), %xmm2
617617
# CHECK-NEXT: 1 1 0.50 psubd %xmm0, %xmm2

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