|
12 | 12 | Therefore, their executions are not blocked by bad-behaving functions / tasks. |
13 | 13 | This important feature is absolutely necessary for mission-critical tasks. |
14 | 14 |
|
15 | | - Version: 1.0.0 |
| 15 | + Version: 1.1.0 |
16 | 16 |
|
17 | 17 | Version Modified By Date Comments |
18 | 18 | ------- ----------- ---------- ----------- |
19 | 19 | 1.0.0 K Hoang 22/08/2022 Initial coding for AVR ATmega164, ATmega324, ATmega644, ATmega1284 with MightyCore |
| 20 | + 1.1.0 K Hoang 22/08/2022 Fix missing code for Timer3 and Timer4 |
20 | 21 | ****************************************************************************************************************************/ |
21 | 22 |
|
22 | 23 | #pragma once |
@@ -71,6 +72,37 @@ void ATmega_TimerInterrupt::init(int8_t timer) |
71 | 72 |
|
72 | 73 | break; |
73 | 74 | #endif |
| 75 | + |
| 76 | + #if defined(TCCR3A) && defined(TCCR3B) && defined(TIMSK3) |
| 77 | + case 3: |
| 78 | + // 16 bit timer |
| 79 | + TCCR3A = 0; |
| 80 | + TCCR3B = 0; |
| 81 | + bitWrite(TCCR3B, WGM32, 1); |
| 82 | + bitWrite(TCCR3B, CS30, 1); |
| 83 | + |
| 84 | + TISR_LOGWARN(F("T3")); |
| 85 | + |
| 86 | + break; |
| 87 | + #endif |
| 88 | + |
| 89 | + #if defined(TCCR4A) && defined(TCCR4B) && defined(TIMSK4) |
| 90 | + case 4: |
| 91 | + // 16 bit timer |
| 92 | + TCCR4A = 0; |
| 93 | + TCCR4B = 0; |
| 94 | + #if defined(WGM42) |
| 95 | + bitWrite(TCCR4B, WGM42, 1); |
| 96 | + #elif defined(CS43) |
| 97 | + // TODO this may not be correct |
| 98 | + bitWrite(TCCR4B, CS43, 1); |
| 99 | + #endif |
| 100 | + bitWrite(TCCR4B, CS40, 1); |
| 101 | + |
| 102 | + TISR_LOGWARN(F("T4")); |
| 103 | + |
| 104 | + break; |
| 105 | + #endif |
74 | 106 | } |
75 | 107 |
|
76 | 108 | _timer = timer; |
@@ -138,16 +170,6 @@ void ATmega_TimerInterrupt::set_OCR() |
138 | 170 | bitWrite(TIMSK4, OCIE4A, 1); |
139 | 171 | break; |
140 | 172 | #endif |
141 | | - |
142 | | -#if defined(OCR5A) && defined(TIMSK5) && defined(OCIE5A) |
143 | | - case 5: |
144 | | - _OCRValueToUse = min(MAX_COUNT_16BIT, _OCRValueRemaining); |
145 | | - OCR5A = _OCRValueToUse; |
146 | | - _OCRValueRemaining -= _OCRValueToUse; |
147 | | - |
148 | | - bitWrite(TIMSK5, OCIE5A, 1); |
149 | | - break; |
150 | | -#endif |
151 | 173 | } |
152 | 174 |
|
153 | 175 | // Flag _OCRValue == 0 => end of long timer |
@@ -326,6 +348,16 @@ bool ATmega_TimerInterrupt::setFrequency(float frequency, timer_callback_p callb |
326 | 348 | TISR_LOGWARN1(F("TCCR1B ="), TCCR1B); |
327 | 349 | } |
328 | 350 | #endif |
| 351 | + |
| 352 | + #if defined(TCCR3B) |
| 353 | + else if (_timer == 3) |
| 354 | + TCCR3B = (TCCR3B & andMask) | _prescalerIndex; //prescalarbits; |
| 355 | + #endif |
| 356 | + |
| 357 | + #if defined(TCCR4B) |
| 358 | + else if (_timer == 4) |
| 359 | + TCCR4B = (TCCR4B & andMask) | _prescalerIndex; //prescalarbits; |
| 360 | + #endif |
329 | 361 |
|
330 | 362 | // Set the OCR for the given timer, |
331 | 363 | // set the toggle count, |
@@ -381,15 +413,6 @@ void ATmega_TimerInterrupt::detachInterrupt(void) |
381 | 413 |
|
382 | 414 | break; |
383 | 415 | #endif |
384 | | - |
385 | | -#if defined(TIMSK5) && defined(OCIE5A) |
386 | | - case 5: |
387 | | - bitWrite(TIMSK5, OCIE5A, 0); |
388 | | - |
389 | | - TISR_LOGWARN(F("Disable T5")); |
390 | | - |
391 | | - break; |
392 | | -#endif |
393 | 416 | } |
394 | 417 |
|
395 | 418 | //sei();//allow interrupts |
@@ -449,15 +472,6 @@ void ATmega_TimerInterrupt::reattachInterrupt(unsigned long duration) |
449 | 472 |
|
450 | 473 | break; |
451 | 474 | #endif |
452 | | - |
453 | | -#if defined(TIMSK5) && defined(OCIE5A) |
454 | | - case 5: |
455 | | - bitWrite(TIMSK5, OCIE5A, 1); |
456 | | - |
457 | | - TISR_LOGWARN(F("Enable T5")); |
458 | | - |
459 | | - break; |
460 | | -#endif |
461 | 475 | } |
462 | 476 |
|
463 | 477 | //sei();//allow interrupts |
@@ -490,6 +504,16 @@ void ATmega_TimerInterrupt::pauseTimer(void) |
490 | 504 | TISR_LOGWARN1(F("TCCR1B ="), TCCR1B); |
491 | 505 | } |
492 | 506 | #endif |
| 507 | + |
| 508 | + #if defined(TCCR3B) |
| 509 | + else if (_timer == 3) |
| 510 | + TCCR3B = (TCCR3B & andMask); |
| 511 | + #endif |
| 512 | + |
| 513 | + #if defined(TCCR4B) |
| 514 | + else if (_timer == 4) |
| 515 | + TCCR4B = (TCCR4B & andMask); |
| 516 | + #endif |
493 | 517 | } |
494 | 518 |
|
495 | 519 | // Just reconnect clock source, continue from the current count |
@@ -517,8 +541,19 @@ void ATmega_TimerInterrupt::resumeTimer(void) |
517 | 541 | TISR_LOGWARN1(F("TCCR1B ="), TCCR1B); |
518 | 542 | } |
519 | 543 | #endif |
| 544 | + |
| 545 | + #if defined(TCCR3B) |
| 546 | + else if (_timer == 3) |
| 547 | + TCCR3B = (TCCR3B & andMask) | _prescalerIndex; //prescalarbits; |
| 548 | + #endif |
| 549 | + |
| 550 | + #if defined(TCCR4B) |
| 551 | + else if (_timer == 4) |
| 552 | + TCCR4B = (TCCR4B & andMask) | _prescalerIndex; //prescalarbits; |
| 553 | + #endif |
520 | 554 | } |
521 | 555 |
|
| 556 | +////////////////////////////////////////////// |
522 | 557 |
|
523 | 558 | #if USE_TIMER_1 |
524 | 559 | #ifndef TIMER1_INSTANTIATED |
|
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