@@ -1041,20 +1041,21 @@ module RangeStage<DeltaSig D, BoundSig<D> Bounds, LangSig<D> LangParam, UtilSig<
10411041 )
10421042 or
10431043 exists (
1044- SemRemExpr rem , SemZeroBound b1 , SemZeroBound b2 , D:: Delta d_max , D:: Delta d1 , D:: Delta d2 ,
1045- boolean fbe1 , boolean fbe2 , D:: Delta od1 , D:: Delta od2 , SemReason r1 , SemReason r2
1044+ SemRemExpr rem , D:: Delta d_max , D:: Delta d1 , D:: Delta d2 , boolean fbe1 , boolean fbe2 ,
1045+ D:: Delta od1 , D:: Delta od2 , SemReason r1 , SemReason r2
10461046 |
10471047 rem = e and
1048+ b instanceof SemZeroBound and
10481049 not ( upper = true and semPositive ( rem .getRightOperand ( ) ) ) and
10491050 not ( upper = true and semPositive ( rem .getLeftOperand ( ) ) ) and
1050- boundedRemExpr ( rem , b1 , true , d1 , fbe1 , od1 , r1 ) and
1051- boundedRemExpr ( rem , b2 , false , d2 , fbe2 , od2 , r2 ) and
1051+ boundedRemExpr ( rem , true , d1 , fbe1 , od1 , r1 ) and
1052+ boundedRemExpr ( rem , false , d2 , fbe2 , od2 , r2 ) and
10521053 (
10531054 if D:: toFloat ( d1 ) .abs ( ) > D:: toFloat ( d2 ) .abs ( )
10541055 then (
1055- b = b1 and d_max = d1 and fromBackEdge = fbe1 and origdelta = od1 and reason = r1
1056+ d_max = d1 and fromBackEdge = fbe1 and origdelta = od1 and reason = r1
10561057 ) else (
1057- b = b2 and d_max = d2 and fromBackEdge = fbe2 and origdelta = od2 and reason = r2
1058+ d_max = d2 and fromBackEdge = fbe2 and origdelta = od2 and reason = r2
10581059 )
10591060 )
10601061 |
@@ -1103,11 +1104,13 @@ module RangeStage<DeltaSig D, BoundSig<D> Bounds, LangSig<D> LangParam, UtilSig<
11031104 )
11041105 }
11051106
1107+ pragma [ nomagic]
11061108 private predicate boundedRemExpr (
1107- SemRemExpr rem , SemZeroBound b , boolean upper , D:: Delta delta , boolean fromBackEdge ,
1108- D :: Delta origdelta , SemReason reason
1109+ SemRemExpr rem , boolean upper , D:: Delta delta , boolean fromBackEdge , D :: Delta origdelta ,
1110+ SemReason reason
11091111 ) {
1110- bounded ( rem .getRightOperand ( ) , b , delta , upper , fromBackEdge , origdelta , reason )
1112+ bounded ( rem .getRightOperand ( ) , any ( SemZeroBound zb ) , delta , upper , fromBackEdge , origdelta ,
1113+ reason )
11111114 }
11121115
11131116 /**
0 commit comments