Skip to content

Commit 76462d9

Browse files
jobitjosephjobitjoseph
authored
Added LANA TNY board #164
The LANA TNY is a development board by Phyx based on the CH32V203G6U6. It is sold through the official Adafruit store: here It is comparable to the already added Adafruit QT Py CH32V203 (in pull request #136) but has some extra GPIO pins exposed and some slightly different pin arrangement. openwch/arduino_core_ch32#164
1 parent 14304e5 commit 76462d9

File tree

1 file changed

+215
-0
lines changed

1 file changed

+215
-0
lines changed

‎variants/CH32V20x/CH32V203G6_LANA_TNY/PeripheralPins.c‎

Lines changed: 215 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,215 @@
1+
/**
2+
*******************************************************************************
3+
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
4+
* All rights reserved.
5+
*
6+
* This software component is licensed by WCH under BSD 3-Clause license,
7+
* the "License"; You may not use this file except in compliance with the
8+
* License. You may obtain a copy of the License at:
9+
* opensource.org/licenses/BSD-3-Clause
10+
*
11+
*******************************************************************************
12+
*/
13+
14+
#include "Arduino.h"
15+
#include "PeripheralPins.h"
16+
17+
/* =====
18+
* Notes:
19+
* - The pins mentioned Px_y_ALTz are alternative possibilities which use other
20+
* HW peripheral instances. You can use them the same way as any other "normal"
21+
* pin (i.e. analogWrite(PA7_ALT1, 128);).
22+
*
23+
* - Commented lines are alternative possibilities which are not used per default.
24+
* If you change them, you will have to know what you do
25+
* =====
26+
*/
27+
28+
//*** ADC ***
29+
#ifdef ADC_MODULE_ENABLED
30+
WEAK const PinMap PinMap_ADC[] = {
31+
{PA_0, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 0)}, // ADC1_IN0
32+
{PA_0_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 0)}, // ADC2_IN0
33+
{PA_1, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 1)}, // ADC1_IN1
34+
{PA_1_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 1)}, // ADC2_IN1
35+
{PA_2, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 2)}, // ADC1_IN2
36+
{PA_2_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 2)}, // ADC2_IN2
37+
{PA_3, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 3)}, // ADC1_IN3
38+
{PA_3_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 3)}, // ADC2_IN3
39+
{PA_4, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 4)}, // ADC1_IN4
40+
{PA_4_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 4)}, // ADC2_IN4
41+
{PA_5, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 5)}, // ADC1_IN5
42+
{PA_5_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 5)}, // ADC2_IN5
43+
{PA_6, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 6)}, // ADC1_IN6
44+
{PA_6_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 6)}, // ADC2_IN6
45+
{PA_7, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 7)}, // ADC1_IN7
46+
{PA_7_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 7)}, // ADC2_IN7
47+
{PB_0, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 8)}, // ADC1_IN8
48+
{PB_0_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 8)}, // ADC2_IN8
49+
{PB_1, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 9)}, // ADC1_IN9
50+
{PB_1_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 9)}, // ADC2_IN9
51+
{NC, NP, 0}
52+
};
53+
#endif
54+
55+
//*** No DAC ***
56+
57+
58+
59+
//*** I2C ***
60+
#ifdef I2C_MODULE_ENABLED
61+
WEAK const PinMap PinMap_I2C_SDA[] = {
62+
{PB_7, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_NONE)},
63+
{PB_9, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_Remap_I2C1_ENABLE)},
64+
{NC, NP, 0}
65+
};
66+
#endif
67+
68+
#ifdef I2C_MODULE_ENABLED
69+
WEAK const PinMap PinMap_I2C_SCL[] = {
70+
{PB_6, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_NONE)},
71+
{PB_8, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_Remap_I2C1_ENABLE)},
72+
{NC, NP, 0}
73+
};
74+
#endif
75+
76+
//*** TIM ***
77+
#ifdef TIM_MODULE_ENABLED
78+
WEAK const PinMap PinMap_TIM[] = {
79+
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 1)}, // TIM2_CH1
80+
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 2)}, // TIM2_CH2
81+
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 3)}, // TIM2_CH3
82+
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 4)}, // TIM2_CH4
83+
84+
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 1)}, // TIM3_CH1
85+
{PA_7, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 2)}, // TIM3_CH2
86+
{PB_0, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 3)}, // TIM3_CH3
87+
{PB_1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 4)}, // TIM3_CH4
88+
89+
{PB_6, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 1)}, // TIM4_CH1
90+
{PB_7, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 2)}, // TIM4_CH2
91+
{PB_8, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 3)}, // TIM4_CH3
92+
{PB_9, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 4)}, // TIM4_CH4
93+
94+
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1
95+
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2
96+
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3
97+
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 4)}, // TIM1_CH4
98+
99+
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1N
100+
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2N
101+
{PA_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3N
102+
{NC, NP, 0}
103+
};
104+
#endif
105+
106+
//*** UART ***
107+
#ifdef UART_MODULE_ENABLED
108+
WEAK const PinMap PinMap_UART_TX[] = {
109+
{PA_9, USART1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
110+
{PB_6, USART1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_Remap_USART1_ENABLE)},
111+
{PA_2, USART2, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
112+
{PB_10,USART3, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
113+
{PC_10,USART3, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_FullRemap_USART3_ENABLE)},
114+
{PB_0, UART4, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
115+
{PA_5, UART4, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_FullRemap_USART4_ENABLE)},
116+
{NC, NP, 0}
117+
};
118+
#endif
119+
120+
#ifdef UART_MODULE_ENABLED
121+
WEAK const PinMap PinMap_UART_RX[] = {
122+
{PA_10, USART1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
123+
{PB_7, USART1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_Remap_USART1_ENABLE)},
124+
{PA_3, USART2, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
125+
{PB_11, USART3, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
126+
{PC_11, USART3, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_FullRemap_USART3_ENABLE)},
127+
{PB_1, UART4, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
128+
{PB_5, UART4, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_FullRemap_USART4_ENABLE)},
129+
{NC, NP, 0}
130+
};
131+
#endif
132+
133+
#ifdef UART_MODULE_ENABLED
134+
WEAK const PinMap PinMap_UART_RTS[] = {
135+
{PA_12, USART1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
136+
{PA_1, USART2, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
137+
{PB_14, USART3, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
138+
{PB_4, UART4, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
139+
{NC, NP, 0}
140+
};
141+
#endif
142+
143+
#ifdef UART_MODULE_ENABLED
144+
WEAK const PinMap PinMap_UART_CTS[] = {
145+
{PA_11, USART1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
146+
{PA_0, USART2, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
147+
{PB_13, USART3, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
148+
{PB_3, UART4, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
149+
{NC, NP, 0}
150+
};
151+
#endif
152+
153+
154+
//*** SPI ***
155+
#ifdef SPI_MODULE_ENABLED
156+
WEAK const PinMap PinMap_SPI_MOSI[] = {
157+
{PA_7, SPI1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
158+
{NC, NP, 0}
159+
};
160+
#endif
161+
162+
#ifdef SPI_MODULE_ENABLED
163+
WEAK const PinMap PinMap_SPI_MISO[] = {
164+
{PA_6, SPI1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_FLOAT, 0, AFIO_NONE)},
165+
{NC, NP, 0}
166+
};
167+
#endif
168+
169+
#ifdef SPI_MODULE_ENABLED
170+
WEAK const PinMap PinMap_SPI_SCLK[] = {
171+
{PA_5, SPI1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
172+
{NC, NP, 0}
173+
};
174+
#endif
175+
176+
#ifdef SPI_MODULE_ENABLED
177+
WEAK const PinMap PinMap_SPI_SSEL[] = {
178+
{PA_4, SPI1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
179+
{NC, NP, 0}
180+
};
181+
#endif
182+
183+
//*** CAN ***
184+
#ifdef CAN_MODULE_ENABLED
185+
WEAK const PinMap PinMap_CAN_RD[] = {
186+
{PA_11, CAN1, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)},
187+
{PB_8, CAN1, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_CAN1_2)},
188+
{NC, NP, 0}
189+
};
190+
#endif
191+
192+
#ifdef CAN_MODULE_ENABLED
193+
WEAK const PinMap PinMap_CAN_TD[] = {
194+
{PA_12, CAN1, CH_PIN_DATA(CH_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE)},
195+
{PB_9, CAN1, CH_PIN_DATA(CH_MODE_AF_PP, GPIO_NOPULL, AFIO_CAN1_2)},
196+
{NC, NP, 0}
197+
};
198+
#endif
199+
200+
//*** No ETHERNET ***
201+
202+
203+
204+
//*** USB ***
205+
#ifdef USB_MODULE_ENABLED
206+
WEAK const PinMap PinMap_USB[] = {
207+
{PA_11, USB, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)}, // USB_DM
208+
{PA_12, USB, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)}, // USB_DP
209+
{NC, NP, 0}
210+
};
211+
#endif
212+
213+
//*** No SD ***
214+
215+

0 commit comments

Comments
 (0)