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[CH32VM00X] Update SDK to apply correct clock #198
I ran the CH32V006 in an Arduino environment and noticed that the delay() function was waiting longer than it should. Assuming that there was a problem with the clock settings, I first looked at the SDK and noticed that it was fixed in the latest SDK, so I synchronized it with this SDK. https://www.wch.cn/downloads/CH32V006EVT_ZIP.html (Ver.1.4) $ cp /path/to/EVT/EXAM/GPIO/GPIO_Toggle/User/* /path/to/arduino_core_ch32/system/CH32VM00X/USER/ $ cd /path/to/arduino_core_ch32/system/CH32VM00X/USER/ $ find . -type f | xargs file |grep CRLF | awk -F: '{print $1}' | xargs nkf -Lu --overwrite   The SDK source code and the code in this repository use different line endings, so I converted them using a command.. openwch/arduino_core_ch32#198
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system/CH32VM00X/USER/system_ch32v00X.c

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -18,19 +18,19 @@
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*/
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//#define SYSCLK_FREQ_8MHz_HSI 8000000
21-
//#define SYSCLK_FREQ_24MHz_HSI HSI_VALUE
22-
// #define SYSCLK_FREQ_48MHz_HSI 48000000
21+
//#define SYSCLK_FREQ_24MHZ_HSI HSI_VALUE
22+
//#define SYSCLK_FREQ_48MHZ_HSI 48000000
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//#define SYSCLK_FREQ_8MHz_HSE 8000000
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//#define SYSCLK_FREQ_24MHz_HSE HSE_VALUE
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//#define SYSCLK_FREQ_48MHz_HSE 48000000
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/* Clock Definitions */
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#ifdef SYSCLK_FREQ_8MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */
30-
#elif defined SYSCLK_FREQ_24MHz_HSI
31-
uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /* System Clock Frequency (Core Clock) */
32-
#elif defined SYSCLK_FREQ_48MHz_HSI
33-
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
30+
#elif defined SYSCLK_FREQ_24MHZ_HSI
31+
uint32_t SystemCoreClock = SYSCLK_FREQ_24MHZ_HSI; /* System Clock Frequency (Core Clock) */
32+
#elif defined SYSCLK_FREQ_48MHZ_HSI
33+
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHZ_HSI; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_8MHz_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSE; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_24MHz_HSE
@@ -49,10 +49,10 @@ static void SetSysClock(void);
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#ifdef SYSCLK_FREQ_8MHz_HSI
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static void SetSysClockTo_8MHz_HSI(void);
52-
#elif defined SYSCLK_FREQ_24MHz_HSI
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static void SetSysClockTo_24MHz_HSI(void);
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#elif defined SYSCLK_FREQ_48MHz_HSI
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static void SetSysClockTo_48MHz_HSI(void);
52+
#elif defined SYSCLK_FREQ_24MHZ_HSI
53+
static void SetSysClockTo_24MHZ_HSI(void);
54+
#elif defined SYSCLK_FREQ_48MHZ_HSI
55+
static void SetSysClockTo_48MHZ_HSI(void);
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#elif defined SYSCLK_FREQ_8MHz_HSE
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static void SetSysClockTo_8MHz_HSE(void);
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#elif defined SYSCLK_FREQ_24MHz_HSE
@@ -194,7 +194,7 @@ static void SetSysClockTo_8MHz_HSI(void)
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FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_0;
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}
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197-
#elif defined SYSCLK_FREQ_24MHz_HSI
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#elif defined SYSCLK_FREQ_24MHZ_HSI
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/*********************************************************************
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* @fn SetSysClockTo_24MHz_HSI
@@ -203,7 +203,7 @@ static void SetSysClockTo_8MHz_HSI(void)
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*
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* @return none
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*/
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static void SetSysClockTo_24MHz_HSI(void)
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static void SetSysClockTo_24MHZ_HSI(void)
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{
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/* HCLK = SYSCLK = PB1 */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
@@ -213,7 +213,7 @@ static void SetSysClockTo_24MHz_HSI(void)
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}
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#elif defined SYSCLK_FREQ_48MHz_HSI
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#elif defined SYSCLK_FREQ_48MHZ_HSI
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/*********************************************************************
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* @fn SetSysClockTo_48MHz_HSI
@@ -222,7 +222,7 @@ static void SetSysClockTo_24MHz_HSI(void)
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*
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* @return none
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*/
225-
static void SetSysClockTo_48MHz_HSI(void)
225+
static void SetSysClockTo_48MHZ_HSI(void)
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{
227227
/* HCLK = SYSCLK = PB1 */
228228
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
@@ -454,3 +454,4 @@ static void SetSysClockTo_48MHz_HSE(void)
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457+

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