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[FEATURE]: Add UART2Wishbone bridge example
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‎examples/uart2wb/quartus/uart2wb_cyc1000.qpf‎

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#-------------------------------------------------------------------------------
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# PROJECT: SIMPLE UART FOR FPGA
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#-------------------------------------------------------------------------------
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# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
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# LICENSE: The MIT License (MIT), please read LICENSE file
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# WEBSITE: https://github.com/jakubcabal/uart-for-fpga
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#-------------------------------------------------------------------------------
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PROJECT_REVISION = "UART2WB_CYC1000"

‎examples/uart2wb/quartus/uart2wb_cyc1000.qsf‎

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#-------------------------------------------------------------------------------
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# PROJECT: SIMPLE UART FOR FPGA
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#-------------------------------------------------------------------------------
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# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
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# LICENSE: The MIT License, please read LICENSE file
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# WEBSITE: https://github.com/jakubcabal/uart-for-fpga
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#-------------------------------------------------------------------------------
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# QUARTUS SETTINGS FILE FOR CYC1000 BOARD
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set_global_assignment -name FAMILY "Cyclone 10 LP"
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set_global_assignment -name DEVICE 10CL025YU256C8G
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set_global_assignment -name TOP_LEVEL_ENTITY UART2WB_FPGA_CYC1000
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# PROJECT VHDL FILES
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set_global_assignment -name VHDL_FILE ../../../rtl/comp/uart_clk_div.vhd
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set_global_assignment -name VHDL_FILE ../../../rtl/comp/uart_parity.vhd
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set_global_assignment -name VHDL_FILE ../../../rtl/comp/uart_debouncer.vhd
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set_global_assignment -name VHDL_FILE ../../../rtl/comp/uart_tx.vhd
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set_global_assignment -name VHDL_FILE ../../../rtl/comp/uart_rx.vhd
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set_global_assignment -name VHDL_FILE ../../../rtl/uart.vhd
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set_global_assignment -name VHDL_FILE ../../common/rst_sync.vhd
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set_global_assignment -name VHDL_FILE ../uart2wbm.vhd
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set_global_assignment -name VHDL_FILE ../uart2wb_fpga_cyc1000.vhd
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# TIMING CONSTRAINTS
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set_global_assignment -name SDC_FILE ./uart2wb_cyc1000.sdc
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# FPGA PINS ASSIGNMENT
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set_location_assignment PIN_M2 -to CLK_12M
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set_location_assignment PIN_N6 -to RST_BTN_N
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set_location_assignment PIN_T7 -to UART_TXD
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set_location_assignment PIN_R7 -to UART_RXD

‎examples/uart2wb/quartus/uart2wb_cyc1000.sdc‎

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#-------------------------------------------------------------------------------
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# PROJECT: SIMPLE UART FOR FPGA
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#-------------------------------------------------------------------------------
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# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
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# LICENSE: The MIT License (MIT), please read LICENSE file
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# WEBSITE: https://github.com/jakubcabal/uart-for-fpga
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#-------------------------------------------------------------------------------
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create_clock -name CLK12M -period 12MHz [get_ports {CLK_12M}]

‎examples/uart2wb/sw/wishbone.py‎

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#!/usr/bin/python
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#-------------------------------------------------------------------------------
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# PROJECT: SIMPLE UART FOR FPGA
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#-------------------------------------------------------------------------------
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# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
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# LICENSE: The MIT License, please read LICENSE file
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# WEBSITE: https://github.com/jakubcabal/uart-for-fpga
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#-------------------------------------------------------------------------------
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import serial
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byteorder="little"
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class wishbone:
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def __init__(self, port="COM1", baudrate=9600):
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self.uart = serial.Serial(port, baudrate, timeout=2)
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print("The UART on " + self.uart.name + " is open.")
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print("The wishbone bus is ready.\n")
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def read(self,addr):
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cmd = 0x0
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cmd = cmd.to_bytes(1,byteorder)
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self.uart.write(cmd)
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addr = addr.to_bytes(2,byteorder)
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self.uart.write(addr)
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rbytes=self.uart.read(1)
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rbytes=self.uart.read(4)
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drd=int.from_bytes(rbytes,byteorder)
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return drd
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def write(self, addr, data):
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cmd = 0x1
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cmd = cmd.to_bytes(1,byteorder)
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self.uart.write(cmd)
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addr = addr.to_bytes(2,byteorder)
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self.uart.write(addr)
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data = data.to_bytes(4,byteorder)
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self.uart.write(data)
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rbytes=self.uart.read(1)
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def close(self):
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self.uart.close()
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if __name__ == '__main__':
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print("Test of access to CSR (control status registers) via UART2WBM module...")
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print("=======================================================================")
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wb = wishbone("COM4")
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print("\nREAD from 0x0:")
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rd = wb.read(0x0)
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print("0x%02X" % rd)
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print("\nREAD from 0x4:")
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rd = wb.read(0x4)
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print("0x%02X" % rd)
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print("\nWRITE 0x12345678 to 0x4.")
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wb.write(0x4,0x12345678)
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print("\nREAD from 0x4:")
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rd = wb.read(0x4)
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print("0x%02X" % rd)
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print("\nWRITE 0xABCDEF12 to 0x4.")
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wb.write(0x4,0xABCDEF12)
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print("\nREAD from 0x4:")
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rd = wb.read(0x4)
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print("0x%02X" % rd)
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print("\nREAD from 0x8844:")
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rd = wb.read(0x8844)
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print("0x%02X" % rd)
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wb.close()
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print("\nThe UART is closed.")

‎examples/uart2wb/uart2wb_fpga_cyc1000.vhd‎

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--------------------------------------------------------------------------------
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-- PROJECT: SIMPLE UART FOR FPGA
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--------------------------------------------------------------------------------
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-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
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-- LICENSE: The MIT License, please read LICENSE file
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-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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-- TOP MODULE OF UART 2 WISHBONE EXAMPLE FOR CYC1000 BOARD
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-- =======================================================
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entity UART2WB_FPGA_CYC1000 is
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Port (
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CLK_12M : in std_logic; -- system clock 12 MHz
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RST_BTN_N : in std_logic; -- low active reset button
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-- UART INTERFACE
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UART_RXD : in std_logic;
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UART_TXD : out std_logic
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);
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end entity;
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architecture RTL of UART2WB_FPGA_CYC1000 is
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signal rst_btn : std_logic;
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signal reset : std_logic;
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signal wb_cyc : std_logic;
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signal wb_stb : std_logic;
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signal wb_we : std_logic;
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signal wb_addr : std_logic_vector(15 downto 0);
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signal wb_dout : std_logic_vector(31 downto 0);
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signal wb_stall : std_logic;
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signal wb_ack : std_logic;
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signal wb_din : std_logic_vector(31 downto 0);
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signal debug_reg_sel : std_logic;
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signal debug_reg_we : std_logic;
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signal debug_reg : std_logic_vector(31 downto 0);
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begin
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rst_btn <= not RST_BTN_N;
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rst_sync_i : entity work.RST_SYNC
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port map (
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CLK => CLK_12M,
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ASYNC_RST => rst_btn,
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SYNCED_RST => reset
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);
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uart2wbm_i : entity work.UART2WBM
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generic map (
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CLK_FREQ => 12e6,
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BAUD_RATE => 9600
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)
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port map (
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CLK => CLK_12M,
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RST => reset,
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-- UART INTERFACE
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UART_TXD => UART_TXD,
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UART_RXD => UART_RXD,
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-- WISHBONE MASTER INTERFACE
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WB_CYC => wb_cyc,
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WB_STB => wb_stb,
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WB_WE => wb_we,
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WB_ADDR => wb_addr,
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WB_DOUT => wb_dout,
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WB_STALL => wb_stall,
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WB_ACK => wb_ack,
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WB_DIN => wb_din
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);
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debug_reg_sel <= '1' when (wb_addr = X"0004") else '0';
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debug_reg_we <= wb_stb and wb_we and debug_reg_sel;
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debug_reg_p : process (CLK_12M)
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begin
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if (rising_edge(CLK_12M)) then
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if (debug_reg_we = '1') then
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debug_reg <= wb_din;
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end if;
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end if;
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end process;
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wb_stall <= '0';
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wb_ack_reg_p : process (CLK_12M)
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begin
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if (rising_edge(CLK_12M)) then
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wb_ack <= wb_cyc and wb_stb;
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end if;
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end process;
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wb_dout_reg_p : process (CLK_12M)
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begin
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if (rising_edge(CLK_12M)) then
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case wb_addr is
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when X"0000" =>
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wb_dout <= X"20210406";
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when X"0004" =>
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wb_dout <= debug_reg;
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when others =>
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wb_dout <= X"DEADCAFE";
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end case;
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end if;
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end process;
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end architecture;

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