UART: Rename all testbench files

Author: jakubcabal

example/uart_loopback_testbench.vhd renamed to example/uart_loopback_tb.vhd

@@ -27,10 +27,10 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
-entity UART_LOOPBACK_TESTBENCH is
-end UART_LOOPBACK_TESTBENCH;
+entity UART_LOOPBACK_TB is
+end UART_LOOPBACK_TB;
 
-architecture FULL of UART_LOOPBACK_TESTBENCH is 
+architecture FULL of UART_LOOPBACK_TB is 
 
 	signal CLK         : std_logic := '0';
 	signal RST_N       : std_logic := '0';

source/comp/uart_fifo_testbench.vhd renamed to source/comp/uart_fifo_tb.vhd

@@ -27,10 +27,10 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
-entity UART_FIFO_TESTBENCH is
-end UART_FIFO_TESTBENCH;
+entity UART_FIFO_TB is
+end UART_FIFO_TB;
 
-architecture FULL of UART_FIFO_TESTBENCH is 
+architecture FULL of UART_FIFO_TB is 
 
 	signal CLK       : std_logic := '0';
 	signal RST       : std_logic := '0';

source/uart_testbench.vhd renamed to source/uart_tb.vhd

@@ -27,10 +27,10 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
-entity UART_TESTBENCH is
-end UART_TESTBENCH;
+entity UART_TB is
+end UART_TB;
 
-architecture FULL of UART_TESTBENCH is 
+architecture FULL of UART_TB is 
 
 	signal CLK         : std_logic := '0';
 	signal RST         : std_logic := '0';