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jakubcabaljakubcabal
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Changed repository name, changed directory structure, added simulation
script and some small bugfixes and edits.
1 parent 4b8d571 commit cc931ff

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6 files changed

+81
-71
lines changed

6 files changed

+81
-71
lines changed

‎source/comp/uart_parity.vhd‎ renamed to ‎rtl/comp/uart_parity.vhd‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
-- MODULE: UART PARITY BIT GENERATOR
55
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
66
-- LICENSE: The MIT License (MIT), please read LICENSE file
7-
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
7+
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
88
--------------------------------------------------------------------------------
99

1010
library IEEE;

‎source/comp/uart_rx.vhd‎ renamed to ‎rtl/comp/uart_rx.vhd‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
-- MODULE: UART RECEIVER
55
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
66
-- LICENSE: The MIT License (MIT), please read LICENSE file
7-
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
7+
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
88
--------------------------------------------------------------------------------
99

1010
library IEEE;

‎source/comp/uart_tx.vhd‎ renamed to ‎rtl/comp/uart_tx.vhd‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
-- MODULE: UART TRANSMITTER
55
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
66
-- LICENSE: The MIT License (MIT), please read LICENSE file
7-
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
7+
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
88
--------------------------------------------------------------------------------
99

1010
library IEEE;
@@ -135,7 +135,7 @@ begin
135135
end generate;
136136

137137
uart_tx_noparity_g : if (PARITY_BIT = "none") generate
138-
tx_parity_bit <= 'Z';
138+
tx_parity_bit <= '0';
139139
end generate;
140140

141141
-- -------------------------------------------------------------------------

‎source/uart.vhd‎ renamed to ‎rtl/uart.vhd‎

Lines changed: 22 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
-- MODULE: UART TOP MODULE
55
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
66
-- LICENSE: The MIT License (MIT), please read LICENSE file
7-
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
7+
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
88
--------------------------------------------------------------------------------
99

1010
library IEEE;
@@ -29,20 +29,20 @@ entity UART is
2929
UART_TXD : out std_logic; -- serial transmit data
3030
UART_RXD : in std_logic; -- serial receive data
3131
-- USER DATA INPUT INTERFACE
32-
DATA_IN : in std_logic_vector(7 downto 0); -- input data
33-
DATA_SEND : in std_logic; -- when DATA_SEND = 1, input data are valid and will be transmit
34-
BUSY : out std_logic; -- when BUSY = 1, transmitter is busy and you must not set DATA_SEND to 1
32+
DIN : in std_logic_vector(7 downto 0); -- data to be transmitted over UART
33+
DIN_VLD : in std_logic; -- when DIN_VLD = 1, DIN is valid and will be accepted for transmiting
34+
BUSY : out std_logic; -- when BUSY = 1, transmitter is busy and DIN can not be accepted
3535
-- USER DATA OUTPUT INTERFACE
36-
DATA_OUT : out std_logic_vector(7 downto 0); -- output data
37-
DATA_VLD : out std_logic; -- when DATA_VLD = 1, output data are valid
38-
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid
36+
DOUT : out std_logic_vector(7 downto 0); -- data received via UART
37+
DOUT_VLD : out std_logic; -- when DOUT_VLD = 1, DOUT is valid (is assert only for one clock cycle)
38+
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid (is assert only for one clock cycle)
3939
);
4040
end UART;
4141

4242
architecture FULL of UART is
4343

44-
constant DIVIDER_VALUE : integer := CLK_FREQ/(16*BAUD_RATE);
45-
constant CLK_CNT_WIDTH : integer := integer(ceil(log2(real(DIVIDER_VALUE))));
44+
constant DIVIDER_VALUE : integer := CLK_FREQ/(16*BAUD_RATE);
45+
constant CLK_CNT_WIDTH : integer := integer(ceil(log2(real(DIVIDER_VALUE))));
4646
constant CLK_CNT_MAX : unsigned := to_unsigned(DIVIDER_VALUE-1, CLK_CNT_WIDTH);
4747

4848
signal uart_clk_cnt : unsigned(CLK_CNT_WIDTH-1 downto 0);
@@ -53,7 +53,7 @@ architecture FULL of UART is
5353
begin
5454

5555
-- -------------------------------------------------------------------------
56-
-- UART CLOCK COUNTER AND CLOCK ENABLE FLAG
56+
-- UART CLOCK COUNTER AND CLOCK ENABLE FLAG
5757
-- -------------------------------------------------------------------------
5858

5959
uart_clk_cnt_p : process (CLK)
@@ -62,7 +62,7 @@ begin
6262
if (RST = '1') then
6363
uart_clk_cnt <= (others => '0');
6464
else
65-
if (uart_clk_cnt = CLK_CNT_MAX) then
65+
if (uart_clk_en = '1') then
6666
uart_clk_cnt <= (others => '0');
6767
else
6868
uart_clk_cnt <= uart_clk_cnt + 1;
@@ -71,21 +71,10 @@ begin
7171
end if;
7272
end process;
7373

74-
uart_clk_en_reg_p : process (CLK)
75-
begin
76-
if (rising_edge(CLK)) then
77-
if (RST = '1') then
78-
uart_clk_en <= '0';
79-
elsif (uart_clk_cnt = CLK_CNT_MAX) then
80-
uart_clk_en <= '1';
81-
else
82-
uart_clk_en <= '0';
83-
end if;
84-
end if;
85-
end process;
74+
uart_clk_en <= '1' when (uart_clk_cnt = CLK_CNT_MAX) else '0';
8675

8776
-- -------------------------------------------------------------------------
88-
-- UART RXD SHIFT REGISTER AND DEBAUNCER
77+
-- UART RXD SHIFT REGISTER AND DEBAUNCER
8978
-- -------------------------------------------------------------------------
9079

9180
use_debouncer_g : if (USE_DEBOUNCER = True) generate
@@ -106,9 +95,9 @@ begin
10695
if (RST = '1') then
10796
uart_rxd_debounced <= '1';
10897
else
109-
uart_rxd_debounced <= uart_rxd_shreg(0) OR
110-
uart_rxd_shreg(1) OR
111-
uart_rxd_shreg(2) OR
98+
uart_rxd_debounced <= uart_rxd_shreg(0) or
99+
uart_rxd_shreg(1) or
100+
uart_rxd_shreg(2) or
112101
uart_rxd_shreg(3);
113102
end if;
114103
end if;
@@ -120,7 +109,7 @@ begin
120109
end generate;
121110

122111
-- -------------------------------------------------------------------------
123-
-- UART TRANSMITTER
112+
-- UART TRANSMITTER
124113
-- -------------------------------------------------------------------------
125114

126115
uart_tx_i: entity work.UART_TX
@@ -134,13 +123,13 @@ begin
134123
UART_CLK_EN => uart_clk_en,
135124
UART_TXD => UART_TXD,
136125
-- USER DATA INPUT INTERFACE
137-
DATA_IN => DATA_IN,
138-
DATA_SEND => DATA_SEND,
126+
DATA_IN => DIN,
127+
DATA_SEND => DIN_VLD,
139128
BUSY => BUSY
140129
);
141130

142131
-- -------------------------------------------------------------------------
143-
-- UART RECEIVER
132+
-- UART RECEIVER
144133
-- -------------------------------------------------------------------------
145134

146135
uart_rx_i: entity work.UART_RX
@@ -154,8 +143,8 @@ begin
154143
UART_CLK_EN => uart_clk_en,
155144
UART_RXD => uart_rxd_debounced,
156145
-- USER DATA OUTPUT INTERFACE
157-
DATA_OUT => DATA_OUT,
158-
DATA_VLD => DATA_VLD,
146+
DATA_OUT => DOUT,
147+
DATA_VLD => DOUT_VLD,
159148
FRAME_ERROR => FRAME_ERROR
160149
);
161150

‎sim/sim.tcl‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
#-------------------------------------------------------------------------------
2+
# PROJECT: SIMPLE UART FOR FPGA
3+
#-------------------------------------------------------------------------------
4+
# MODULE: SIMULATION TCL SCRIPT FOR MODELSIM
5+
# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
6+
# LICENSE: The MIT License (MIT), please read LICENSE file
7+
# WEBSITE: https://github.com/jakubcabal/uart-for-fpga
8+
#-------------------------------------------------------------------------------
9+
10+
# Compile VHDL files
11+
vcom ../rtl/comp/uart_parity.vhd
12+
vcom ../rtl/comp/uart_tx.vhd
13+
vcom ../rtl/comp/uart_rx.vhd
14+
vcom ../rtl/uart.vhd
15+
vcom ./uart_tb.vhd
16+
17+
# Load testbench
18+
vsim work.uart_tb
19+
20+
# Setup and start simulation
21+
add wave *
22+
#add wave sim:/uart_tb/utt/*
23+
run 10 us

‎source/uart_tb.vhd‎ renamed to ‎sim/uart_tb.vhd‎

Lines changed: 32 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
-- MODULE: TESTBANCH OF UART TOP MODULE
55
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
66
-- LICENSE: The MIT License (MIT), please read LICENSE file
7-
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
7+
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
88
--------------------------------------------------------------------------------
99

1010
library IEEE;
@@ -16,16 +16,16 @@ end UART_TB;
1616

1717
architecture FULL of UART_TB is
1818

19-
signal CLK : std_logic := '0';
20-
signal RST : std_logic := '0';
19+
signal CLK : std_logic;
20+
signal RST : std_logic;
2121
signal tx_uart : std_logic;
22-
signal rx_uart : std_logic := '1';
23-
signal data_vld : std_logic;
24-
signal data_out : std_logic_vector(7 downto 0);
25-
signal frame_error : std_logic;
26-
signal data_send : std_logic;
22+
signal rx_uart : std_logic;
23+
signal din : std_logic_vector(7 downto 0);
24+
signal din_vld : std_logic;
2725
signal busy : std_logic;
28-
signal data_in : std_logic_vector(7 downto 0);
26+
signal dout : std_logic_vector(7 downto 0);
27+
signal dout_vld : std_logic;
28+
signal frame_error : std_logic;
2929

3030
constant clk_period : time := 20 ns;
3131
constant uart_period : time := 8680.56 ns;
@@ -47,13 +47,13 @@ begin
4747
UART_TXD => tx_uart,
4848
UART_RXD => rx_uart,
4949
-- USER DATA INPUT INTERFACE
50-
DATA_OUT => data_out,
51-
DATA_VLD => data_vld,
52-
FRAME_ERROR => frame_error,
53-
-- USER DATA OUTPUT INTERFACE
54-
DATA_IN => data_in,
55-
DATA_SEND => data_send,
50+
DIN => din,
51+
DIN_VLD => din_vld,
5652
BUSY => busy
53+
-- USER DATA OUTPUT INTERFACE
54+
DOUT => dout,
55+
DOUT_VLD => dout_vld,
56+
FRAME_ERROR => frame_error,
5757
);
5858

5959
clk_process : process
@@ -64,13 +64,18 @@ begin
6464
wait for clk_period/2;
6565
end process;
6666

67-
test_rx_uart : process
67+
rst_gen_p : process
6868
begin
69-
rx_uart <= '1';
7069
RST <= '1';
7170
wait for 100 ns;
72-
RST <= '0';
71+
RST <= '0';
72+
end process;
73+
74+
test_rx_uart : process
75+
begin
76+
rx_uart <= '1';
7377

78+
wait until RST = '0';
7479
wait until rising_edge(CLK);
7580

7681
rx_uart <= '0'; -- start bit
@@ -101,34 +106,27 @@ begin
101106

102107
test_tx_uart : process
103108
begin
104-
data_send <= '0';
105-
RST <= '1';
106-
wait for 100 ns;
107-
RST <= '0';
109+
din_vld <= '0';
108110

111+
wait until RST = '0';
109112
wait until rising_edge(CLK);
110-
111-
data_send <= '1';
112-
data_in <= data_value;
113+
din_vld <= '1';
114+
din <= data_value;
113115

114116
wait until rising_edge(CLK);
115-
116-
data_send <= '0';
117+
din_vld <= '0';
117118

118119
wait until rising_edge(CLK);
119-
120120
wait for 80 us;
121-
wait until rising_edge(CLK);
122-
123-
data_send <= '1';
124-
data_in <= data_value2;
125121

126122
wait until rising_edge(CLK);
127-
128-
data_send <= '0';
123+
din_vld <= '1';
124+
din <= data_value2;
129125

130126
wait until rising_edge(CLK);
127+
din_vld <= '0';
131128

129+
wait until rising_edge(CLK);
132130
wait;
133131

134132
end process;

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