[FEATURE]: Add Parity Error output port

Author: jakubcabal

examples/loopback/uart_loopback_cyc1000.vhd

@@ -57,19 +57,20 @@ begin
         USE_DEBOUNCER => USE_DEBOUNCER
     )
     port map (
-        CLK         => CLK_12M,
-        RST         => reset,
+        CLK          => CLK_12M,
+        RST          => reset,
         -- UART INTERFACE
-        UART_TXD    => UART_TXD,
-        UART_RXD    => UART_RXD,
-        -- USER DATA OUTPUT INTERFACE
-        DOUT        => data,
-        DOUT_VLD    => valid,
-        FRAME_ERROR => open,
+        UART_TXD     => UART_TXD,
+        UART_RXD     => UART_RXD,
         -- USER DATA INPUT INTERFACE
-        DIN         => data,
-        DIN_VLD     => valid,
-        DIN_RDY     => open
+        DIN          => data,
+        DIN_VLD      => valid,
+        DIN_RDY      => open,
+        -- USER DATA OUTPUT INTERFACE
+        DOUT         => data,
+        DOUT_VLD     => valid,
+        FRAME_ERROR  => open,
+        PARITY_ERROR => open
     );
 
 end architecture;

examples/uart2wb/uart2wbm.vhd

@@ -260,19 +260,20 @@ begin
         USE_DEBOUNCER => True
     )
     port map (
-        CLK         => CLK,
-        RST         => RST,
+        CLK          => CLK,
+        RST          => RST,
         -- UART INTERFACE
-        UART_TXD    => UART_TXD,
-        UART_RXD    => UART_RXD,
-        -- USER DATA OUTPUT INTERFACE
-        DOUT        => uart_dout,
-        DOUT_VLD    => uart_dout_vld,
-        FRAME_ERROR => open,
+        UART_TXD     => UART_TXD,
+        UART_RXD     => UART_RXD,
         -- USER DATA INPUT INTERFACE
-        DIN         => uart_din,
-        DIN_VLD     => uart_din_vld,
-        DIN_RDY     => uart_din_rdy
+        DIN          => uart_din,
+        DIN_VLD      => uart_din_vld,
+        DIN_RDY      => uart_din_rdy,
+        -- USER DATA OUTPUT INTERFACE
+        DOUT         => uart_dout,
+        DOUT_VLD     => uart_dout_vld,
+        FRAME_ERROR  => open,
+        PARITY_ERROR => open
     );
 
 end architecture;

rtl/uart.vhd

@@ -35,6 +35,7 @@ use IEEE.MATH_REAL.ALL;
     -- Added better simulation with automatic checking of transactions.
     -- Little code cleaning and code optimization.
     -- Added UART2WB bridge example (access to WB registers via UART).
+    -- Added Parity Error output.
 
 entity UART is
     Generic (
@@ -45,19 +46,20 @@ entity UART is
     );
     Port (
         -- CLOCK AND RESET
-        CLK         : in  std_logic; -- system clock
-        RST         : in  std_logic; -- high active synchronous reset
+        CLK          : in  std_logic; -- system clock
+        RST          : in  std_logic; -- high active synchronous reset
         -- UART INTERFACE
-        UART_TXD    : out std_logic; -- serial transmit data
-        UART_RXD    : in  std_logic; -- serial receive data
+        UART_TXD     : out std_logic; -- serial transmit data
+        UART_RXD     : in  std_logic; -- serial receive data
         -- USER DATA INPUT INTERFACE
-        DIN         : in  std_logic_vector(7 downto 0); -- input data to be transmitted over UART
-        DIN_VLD     : in  std_logic; -- when DIN_VLD = 1, input data (DIN) are valid
-        DIN_RDY     : out std_logic; -- when DIN_RDY = 1, transmitter is ready and valid input data will be accepted for transmiting
+        DIN          : in  std_logic_vector(7 downto 0); -- input data to be transmitted over UART
+        DIN_VLD      : in  std_logic; -- when DIN_VLD = 1, input data (DIN) are valid
+        DIN_RDY      : out std_logic; -- when DIN_RDY = 1, transmitter is ready and valid input data will be accepted for transmiting
         -- USER DATA OUTPUT INTERFACE
-        DOUT        : out std_logic_vector(7 downto 0); -- output data received via UART
-        DOUT_VLD    : out std_logic; -- when DOUT_VLD = 1, output data (DOUT) are valid (is assert only for one clock cycle)
-        FRAME_ERROR : out std_logic  -- when FRAME_ERROR = 1, stop bit was invalid (is assert only for one clock cycle)
+        DOUT         : out std_logic_vector(7 downto 0); -- output data received via UART
+        DOUT_VLD     : out std_logic; -- when DOUT_VLD = 1, output data (DOUT) are valid (is assert only for one clock cycle)
+        FRAME_ERROR  : out std_logic; -- when FRAME_ERROR = 1, stop bit was invalid (is assert only for one clock cycle)
+        PARITY_ERROR : out std_logic  -- when PARITY_ERROR = 1, parity bit was invalid (is assert only for one clock cycle)
     );
 end entity;
 
@@ -144,7 +146,7 @@ begin
         DOUT         => DOUT,
         DOUT_VLD     => DOUT_VLD,
         FRAME_ERROR  => FRAME_ERROR,
-        PARITY_ERROR => open
+        PARITY_ERROR => PARITY_ERROR
     );
 
     -- -------------------------------------------------------------------------

sim/uart_tb.vhd

@@ -40,7 +40,9 @@ architecture SIM of UART_TB is
     signal monitor_txd_start_bit     : std_logic := '0';
     signal monitor_txd_stop_bit      : std_logic := '0';
 
-    signal frame_error : std_logic;
+    signal frame_error  : std_logic;
+    signal parity_error : std_logic;
+
     signal rand_int : integer := 0;
 
     constant CLK_FREQ      : natural := 50e6;
@@ -98,7 +100,7 @@ architecture SIM of UART_TB is
         -- move to middle of stop bit
         wait for UART_PER/2;
         if (UART_RXD = '0') then
-            report "Invalid stop bit in UART_MONITOR!" severity failure;
+            report "======== INVALID STOP BIT IN UART_MONITOR! ========" severity failure;
         end if;
         UART_STOP_BIT <= '0';
         -- in middle of stop bit move to resync (wait for start bit)
@@ -116,27 +118,27 @@ begin
         wait for CLK_PERIOD;
     end process;
 
-
     utt : entity work.UART
     generic map (
         CLK_FREQ    => CLK_FREQ,
         BAUD_RATE   => BAUD_RATE,
         PARITY_BIT  => "none" -- parity bit is not supported in this simulation
     )
     port map (
-        CLK         => CLK,
-        RST         => RST,
+        CLK          => CLK,
+        RST          => RST,
         -- UART INTERFACE
-        UART_TXD    => monitor_txd,
-        UART_RXD    => driver_rxd,
+        UART_TXD     => monitor_txd,
+        UART_RXD     => driver_rxd,
         -- USER DATA INPUT INTERFACE
-        DIN         => driver_din,
-        DIN_VLD     => driver_din_vld,
-        DIN_RDY     => driver_din_rdy,
+        DIN          => driver_din,
+        DIN_VLD      => driver_din_vld,
+        DIN_RDY      => driver_din_rdy,
         -- USER DATA OUTPUT INTERFACE
-        DOUT        => monitor_dout,
-        DOUT_VLD    => monitor_dout_vld,
-        FRAME_ERROR => frame_error
+        DOUT         => monitor_dout,
+        DOUT_VLD     => monitor_dout_vld,
+        FRAME_ERROR  => frame_error,
+        PARITY_ERROR => parity_error
     );
 
     clk_gen_p : process
@@ -181,7 +183,7 @@ begin
             if (monitor_dout = monitor_dout_expected) then
                 --report "Transaction on DOUT port is OK." severity note;
             else
-                report "Unexpected transaction on DOUT port!" severity failure;
+                report "======== UNEXPECTED TRANSACTION ON DOUT PORT! ========" severity failure;
             end if;
             wait for CLK_PERIOD;
         end loop;
@@ -221,7 +223,7 @@ begin
             if (monitor_txd_dout = monitor_txd_dout_expected) then
                 --report "Transaction on UART_TXD port is OK." severity note;
             else
-                report "Unexpected transaction on UART_TXD port!" severity failure;
+                report "======== UNEXPECTED TRANSACTION ON UART_TXD PORT! ========" severity failure;
             end if;
         end loop;
         monitor_txd_done <= '1';
@@ -238,7 +240,7 @@ begin
         v_test_done := driver_rxd_done and monitor_dout_done and driver_din_done and monitor_txd_done;
         if (v_test_done = '1') then
             wait for 100*CLK_PERIOD;
-            report "Simulation successfully completed." severity failure;
+            report "======== SIMULATION SUCCESSFULLY COMPLETED! ========" severity failure;
         end if;
         wait for CLK_PERIOD;
     end process;