UART: optimalizations, add frame error detect, etc.

Author: jakubcabal

README.md

@@ -2,15 +2,15 @@
 
 Simple UART (Universal Asynchronous Receiver & Transmitter) module for serial communication with an FPGA. The UART module was implemented using VHDL.
 
-**The default settings are 115200 Baud rate, 8 Data bits, 1 Stop bit, No parity, disable input data FIFO.**
+**The default settings are 115200 baud rate, 8 data bits, 1 stop bit, no parity, disable input data FIFO, 50 MHz system clock.**
 
 The UART module was tested in hardware. In the near future it will be implemented generic support for parity bit and set the number of stop bits. Stay tuned!
 
 **Synthesis resource usage summary:**
 
-Input data FIFO | Logic element (LUT) | Registers (FF) | Block RAM (BRAM)
+Input FIFO | LE (LUT) | FF | BRAM
 --- | --- | --- | ---
-disable | 77 | 51 | 0
-enable | 116 | 68 | 1
+disable | 72 | 46 | 0
+enable | 110 | 63 | 1
 
-*Synthesis was performed using Quartus II 64-Bit Version 13.0.1 with default settings for Cyclone II.*
+*Synthesis was performed using Quartus II 64-Bit Version 13.0.1 with default settings for FPGA Altera Cyclone II.*

example/uart_loopback.vhd

@@ -29,7 +29,7 @@ use IEEE.NUMERIC_STD.ALL;
 
 entity UART_LOOPBACK is
     Generic (
-        BAUD_RATE  : integer := 9600;
+        BAUD_RATE  : integer := 115200;
         DATA_BITS  : integer := 8;
         CLK_FREQ   : integer := 50e6;
         INPUT_FIFO : boolean := True;
@@ -40,42 +40,62 @@ entity UART_LOOPBACK is
         RST_N      : in  std_logic; -- low active synchronous reset
         -- UART INTERFACE
         TX_UART    : out std_logic;
-        RX_UART    : in  std_logic
+        RX_UART    : in  std_logic;
+        -- DEBUG INTERFACE
+        BUSY       : out std_logic;
+        FRAME_ERR  : out std_logic;
+        DATA_VLD   : out std_logic
     );
 end UART_LOOPBACK;
 
 architecture FULL of UART_LOOPBACK is
 
-    -- signals
-    signal data  : std_logic_vector(DATA_BITS-1 downto 0);
-    signal valid : std_logic;
-    signal reset : std_logic;
+    signal data        : std_logic_vector(DATA_BITS-1 downto 0);
+    signal valid       : std_logic;
+    signal reset       : std_logic;
+    signal frame_error : std_logic;
+    signal send        : std_logic;
 
 begin
 
 	reset <= not RST_N;
+	send <= valid WHEN (frame_error = '0') ELSE '0';
 
 	uart_i: entity work.UART
     generic map (
-        BAUD_RATE  => BAUD_RATE,  -- baud rate value, default is 9600
-        DATA_BITS  => DATA_BITS,  -- legal values: 5,6,7,8, default is 8 dat bits
-        CLK_FREQ   => CLK_FREQ,   -- set system clock frequency in Hz, default is 50 MHz
-        INPUT_FIFO => INPUT_FIFO, -- enable input data FIFO, default is disable
-        FIFO_DEPTH => FIFO_DEPTH  -- set depth of input data FIFO, default is 256 items
+        BAUD_RATE   => BAUD_RATE,
+        DATA_BITS   => DATA_BITS,
+        CLK_FREQ    => CLK_FREQ,
+        INPUT_FIFO  => INPUT_FIFO,
+        FIFO_DEPTH  => FIFO_DEPTH
     )
     port map (
-        CLK       => CLK,   -- system clock
-        RST       => reset, -- high active synchronous reset
+        CLK         => CLK,
+        RST         => reset,
         -- UART INTERFACE
-        TX_UART   => TX_UART,
-        RX_UART   => RX_UART,
+        TX_UART     => TX_UART,
+        RX_UART     => RX_UART,
         -- USER DATA OUTPUT INTERFACE
-        DATA_OUT  => data,
-        DATA_VLD  => valid, -- when DATA_VLD = 1, data on DATA_OUT are valid
+        DATA_OUT    => data,
+        DATA_VLD    => valid,
+        FRAME_ERROR => frame_error,
         -- USER DATA INPUT INTERFACE
-        DATA_IN   => data,
-        DATA_SEND => valid, -- when DATA_SEND = 1, data on DATA_IN will be transmit
-        BUSY      => open   -- when BUSY = 1, you must not set DATA_SEND to 1
+        DATA_IN     => data,
+        DATA_SEND   => send,
+        BUSY        => BUSY
     );
 
+    frame_err_gen : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (reset = '1') then
+                FRAME_ERR <= '0';
+            elsif (valid = '1') then
+            	FRAME_ERR <= frame_error;
+            end if;
+        end if;
+    end process;
+
+    DATA_VLD <= valid;
+
 end FULL;

example/uart_loopback_testbench.vhd

@@ -0,0 +1,135 @@
+-- The MIT License (MIT)
+--
+-- Copyright (c) 2015 Jakub Cabal
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+-- 
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+-- SOFTWARE.
+--
+-- Website: https://github.com/jakubcabal/uart_for_fpga
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+ 
+entity UART_LOOPBACK_TESTBENCH is
+end UART_LOOPBACK_TESTBENCH;
+ 
+architecture FULL of UART_LOOPBACK_TESTBENCH is 
+
+	signal CLK         : std_logic := '0';
+	signal RST_N       : std_logic := '0';
+	signal tx_uart     : std_logic;
+	signal rx_uart     : std_logic := '1';
+	signal data_vld    : std_logic;
+	signal frame_error : std_logic;
+	signal busy        : std_logic;
+
+   	constant clk_period  : time := 20 ns;
+	constant uart_period : time := 8696 ns;
+	constant data_value  : std_logic_vector(7 downto 0) := "10100111";
+	constant data_value2 : std_logic_vector(7 downto 0) := "00110110";
+ 
+begin
+ 
+	utt: entity work.UART_LOOPBACK
+    generic map (
+        BAUD_RATE   => 115200, -- baud rate value
+        DATA_BITS   => 8,      -- legal values: 5,6,7,8
+        CLK_FREQ    => 50e6,   -- set system clock frequency in Hz
+        INPUT_FIFO  => True,   -- enable input data FIFO
+        FIFO_DEPTH  => 256	   -- set depth of input data FIFO
+    )
+    port map (
+        CLK         => CLK,
+        RST_N       => RST_N,
+        -- UART RS232 INTERFACE
+        TX_UART     => tx_uart,
+        RX_UART     => rx_uart,
+        -- DEBUG INTERFACE
+        BUSY        => busy,
+        FRAME_ERR   => frame_error,
+        DATA_VLD    => data_vld
+    );
+
+	clk_process : process
+	begin
+		CLK <= '0';
+		wait for clk_period/2;
+		CLK <= '1';
+		wait for clk_period/2;
+	end process;
+
+	test_rx_uart : process
+	begin
+		rx_uart <= '1';
+		RST_N <= '0';
+		wait for 100 ns;
+      	RST_N <= '1';
+
+		wait for uart_period;
+
+		rx_uart <= '0'; -- start bit
+		wait for uart_period;
+
+		for i in 0 to 7 loop
+			rx_uart <= data_value(i); -- data bits
+			wait for uart_period;
+		end loop;
+
+		rx_uart <= '1'; -- stop bit
+		wait for uart_period;
+
+		rx_uart <= '0'; -- start bit
+		wait for uart_period;
+
+		for i in 0 to 7 loop
+			rx_uart <= data_value2(i); -- data bits
+			wait for uart_period;
+		end loop;
+
+		rx_uart <= '1'; -- stop bit
+		wait for uart_period;
+
+		rx_uart <= '0'; -- start bit
+		wait for uart_period;
+
+		for i in 0 to 7 loop
+			rx_uart <= data_value(i); -- data bits
+			wait for uart_period;
+		end loop;
+
+		rx_uart <= '1'; -- stop bit
+		wait for uart_period;
+
+		rx_uart <= '0'; -- start bit
+		wait for uart_period;
+
+		for i in 0 to 7 loop
+			rx_uart <= data_value2(i); -- data bits
+			wait for uart_period;
+		end loop;
+
+		rx_uart <= '1'; -- stop bit
+		wait for uart_period;
+
+		wait;
+
+	end process;
+
+end FULL;