@@ -1663,7 +1663,7 @@ MachineInstr *Z80InstrInfo::optimizeLoadInstr(MachineInstr &MI,
16631663 Register &FoldAsLoadDefReg,
16641664 MachineInstr *&DefMI) const {
16651665 // Check whether we can move DefMI here.
1666- DefMI = MRI->getVRegDef (FoldAsLoadDefReg);
1666+ DefMI = MRI->getUniqueVRegDef (FoldAsLoadDefReg);
16671667 bool SawStore = false ;
16681668 if (!DefMI || !DefMI->isSafeToMove (nullptr , SawStore))
16691669 return nullptr ;
@@ -1734,18 +1734,29 @@ MachineInstr *Z80InstrInfo::foldMemoryOperandImpl(
17341734
17351735 unsigned Opc;
17361736 unsigned OpSize = 1 ;
1737- switch (MI.getOpcode ()) {
1738- case Z80::BIT8bg: Opc = IsOff ? Z80::BIT8bo : Z80::BIT8bp; break ;
1739- case Z80::ADD8ar: Opc = IsOff ? Z80::ADD8ao : Z80::ADD8ap; break ;
1740- case Z80::ADC8ar: Opc = IsOff ? Z80::ADC8ao : Z80::ADC8ap; break ;
1741- case Z80::SUB8ar: Opc = IsOff ? Z80::SUB8ao : Z80::SUB8ap; break ;
1742- case Z80::SBC8ar: Opc = IsOff ? Z80::SBC8ao : Z80::SBC8ap; break ;
1743- case Z80::AND8ar: Opc = IsOff ? Z80::AND8ao : Z80::AND8ap; break ;
1744- case Z80::XOR8ar: Opc = IsOff ? Z80::XOR8ao : Z80::XOR8ap; break ;
1745- case Z80:: OR8ar: Opc = IsOff ? Z80:: OR8ao : Z80:: OR8ap; break ;
1746- case Z80::TST8ar: Opc = IsOff ? Z80::TST8ao : Z80::TST8ap; break ;
1747- case TargetOpcode::COPY: Opc = IsOff ? Z80::LD8ro : Z80::LD8rp; break ;
1737+ switch (OpNum) {
17481738 default : return nullptr ;
1739+ case 0 :
1740+ switch (MI.getOpcode ()) {
1741+ default : return nullptr ;
1742+ case TargetOpcode:: COPY: Opc = IsOff ? Z80:: LD8or : Z80:: LD8pr; break ;
1743+ }
1744+ break ;
1745+ case 1 :
1746+ switch (MI.getOpcode ()) {
1747+ default : return nullptr ;
1748+ case Z80::BIT8bg: Opc = IsOff ? Z80::BIT8bo : Z80::BIT8bp; break ;
1749+ case Z80::ADD8ar: Opc = IsOff ? Z80::ADD8ao : Z80::ADD8ap; break ;
1750+ case Z80::ADC8ar: Opc = IsOff ? Z80::ADC8ao : Z80::ADC8ap; break ;
1751+ case Z80::SUB8ar: Opc = IsOff ? Z80::SUB8ao : Z80::SUB8ap; break ;
1752+ case Z80::SBC8ar: Opc = IsOff ? Z80::SBC8ao : Z80::SBC8ap; break ;
1753+ case Z80::AND8ar: Opc = IsOff ? Z80::AND8ao : Z80::AND8ap; break ;
1754+ case Z80::XOR8ar: Opc = IsOff ? Z80::XOR8ao : Z80::XOR8ap; break ;
1755+ case Z80:: OR8ar: Opc = IsOff ? Z80:: OR8ao : Z80:: OR8ap; break ;
1756+ case Z80::TST8ar: Opc = IsOff ? Z80::TST8ao : Z80::TST8ap; break ;
1757+ case TargetOpcode:: COPY: Opc = IsOff ? Z80:: LD8ro : Z80:: LD8rp; break ;
1758+ }
1759+ break ;
17491760 }
17501761
17511762 if (Size && Size < OpSize)
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