Merge with upstream.

Author: jacobly0

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

@@ -226,6 +226,10 @@ class CallLowering {
   };
 
   struct ValueHandler {
+    MachineIRBuilder &MIRBuilder;
+    MachineRegisterInfo &MRI;
+    const bool IsIncomingArgumentHandler;
+
     ValueHandler(bool IsIncoming, MachineIRBuilder &MIRBuilder,
                  MachineRegisterInfo &MRI)
         : MIRBuilder(MIRBuilder), MRI(MRI),
@@ -308,13 +312,6 @@ class CallLowering {
                             unsigned MaxSizeBits = 0);
 
     virtual bool finalize(CCState &State) { return true; }
-
-    MachineIRBuilder &MIRBuilder;
-    MachineRegisterInfo &MRI;
-    CCAssignFn *AssignFn;
-
-  private:
-    bool IsIncomingArgumentHandler;
   };
 
   /// Base class for ValueHandlers used for arguments coming into the current

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

@@ -185,7 +185,7 @@ class LegalizerHelper {
   void extractParts(Register Reg, LLT Ty, int NumParts,
                     SmallVectorImpl<Register> &VRegs);
 
-  /// Version which handles irregular splits.
+  /// Versions which handle irregular splits.
   bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
                     LLT &LeftoverTy,
                     SmallVectorImpl<Register> &VRegs,

llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

@@ -1215,17 +1215,12 @@ class LegalizerInfo {
   }
 
   virtual LegalizerHelper::LegalizeResult
-  legalizeCustomMaybeLegal(LegalizerHelper &Helper, MachineInstr &MI) const {
+  legalizeCustomMaybeLegal(LegalizerHelper &Helper, MachineInstr &MI,
+                           LostDebugLocObserver &LocObserver) const {
     return legalizeCustom(Helper, MI) ? LegalizerHelper::Legalized
                                       : LegalizerHelper::UnableToLegalize;
   }
 
-  virtual LegalizerHelper::LegalizeResult
-  legalizeCustomMaybeLegal(LegalizerHelper &Helper, MachineInstr &MI,
-                           LostDebugLocObserver &) const {
-    return legalizeCustomMaybeLegal(Helper, MI);
-  }
-
   /// \returns true if MI is either legal or has been legalized and false if not
   /// legal.
   /// Return true if MI is either legal or has been legalized and false

llvm/include/llvm/Support/MachineValueType.h

@@ -1083,7 +1083,7 @@ namespace llvm {
     /// base size.
     TypeSize getStoreSize() const {
       TypeSize BaseSize = getSizeInBits();
-      return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()};
+      return {divideCeil(BaseSize.getKnownMinSize(), 8), BaseSize.isScalable()};
     }
 
     /// Return the number of bits overwritten by a store of the specified value

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

@@ -716,6 +716,8 @@ bool CallLowering::handleAssignments(ValueHandler &Handler,
         ArgReg = MRI.createGenericVirtualRegister(p0);
       else {
         MachineFrameInfo &MFI = MF.getFrameInfo();
+        // TODO: The memory size may be larger than the value we need to
+        // store. We may need to adjust the offset for big endian targets.
         LLT MemTy = Handler.getStackValueStoreType(DL, VA, Args[i].Flags[0]);
         int FI = MFI.CreateStackObject(MemTy.getSizeInBytes(),
                                        DL.getPrefTypeAlign(Args[i].Ty), false);
@@ -855,6 +857,8 @@ bool CallLowering::handleAssignments(ValueHandler &Handler,
 
       if (VA.getLocInfo() == CCValAssign::Indirect) {
         Register AddrReg;
+        // TODO: The memory size may be larger than the value we need to
+        // store. We may need to adjust the offset for big endian targets.
         LLT MemTy = Handler.getStackValueStoreType(DL, VA, Args[i].Flags[0]);
         LLT sIndex = LLT::scalar(DL.getIndexSizeInBits(0));
         MIRBuilder.materializePtrAdd(AddrReg, Args[i].Regs[0], sIndex,

llvm/lib/CodeGen/GlobalISel/Legalizer.cpp

@@ -103,7 +103,6 @@ static bool isArtifact(const MachineInstr &MI) {
   case TargetOpcode::G_CONCAT_VECTORS:
   case TargetOpcode::G_BUILD_VECTOR:
   case TargetOpcode::G_EXTRACT:
-  case TargetOpcode::G_INSERT:
     return true;
   }
 }

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

@@ -4227,8 +4227,8 @@ LegalizerHelper::reduceLoadStoreWidth(GLoadStore &LdStMI, unsigned TypeIdx,
 
       MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
 
-      MachineMemOperand *NewMMO =
-          MF.getMachineMemOperand(&MMO, ByteOffset, PartTy);
+            MachineMemOperand *NewMMO =
+                MF.getMachineMemOperand(&MMO, ByteOffset, PartTy);
 
       if (IsLoad) {
         Register Dst = MRI.createGenericVirtualRegister(PartTy);

llvm/lib/Target/Z80/GISel/Z80CallLowering.cpp

@@ -540,6 +540,7 @@ bool Z80CallLowering::lowerTailCall(MachineIRBuilder &MIRBuilder,
   // by -tailcallopt. For sibcalls, the memory operands for the call are
   // already available in the caller's incoming argument space.
   unsigned NumBytes = 0;
+  OutgoingValueAssigner CalleeAssigner(CC_Z80);
   if (!IsSibCall) {
     // We aren't sibcalling, so we need to compute FPDiff. We need to do this
     // before handling assignments, because FPDiff must be known for memory
@@ -548,21 +549,19 @@ bool Z80CallLowering::lowerTailCall(MachineIRBuilder &MIRBuilder,
     SmallVector<CCValAssign, 16> OutLocs;
     CCState OutInfo(Info.CallConv, false, MF, OutLocs, F.getContext());
 
-    OutgoingValueAssigner CalleeAssigner(CC_Z80);
-    determineAssignments(CalleeAssigner, OutArgs, OutInfo);
+    if (!determineAssignments(CalleeAssigner, OutArgs, OutInfo))
+      return false;
 
     // FPDiff will be negative if this tail call requires more space than we
     // would automatically have in our incoming argument space. Positive if we
     // actually shrink the stack.
     FPDiff = NumReusableBytes - NumBytes;
   }
 
-  OutgoingValueAssigner Assigner(CC_Z80);
   // Do the actual argument marshalling.
-  SmallVector<unsigned, 8> PhysRegs;
   TailCallArgHandler Handler(MIRBuilder, MRI, MIB, FPDiff);
-  if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
-                                     Info.CallConv, Info.IsVarArg))
+  if (!determineAndHandleAssignments(Handler, CalleeAssigner, OutArgs,
+                                     MIRBuilder, Info.CallConv, Info.IsVarArg))
     return false;
 
   // If we have -tailcallopt, we need to adjust the stack. We'll do the call
@@ -684,23 +683,11 @@ bool Z80CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
   // implicit-define of the call instruction.
 
   if (!InArgs.empty()) {
-    SmallVector<Register, 8> NewRegs;
-
     OutgoingValueAssigner Assigner(RetCC_Z80);
     CallReturnHandler Handler(MIRBuilder, MRI, MIB);
     if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
                                        Info.CallConv, Info.IsVarArg))
       return false;
-
-    if (!NewRegs.empty()) {
-      SmallVector<uint64_t, 8> Indices;
-      uint64_t Index = 0;
-      for (Register Reg : NewRegs) {
-        Indices.push_back(Index);
-        Index += MRI.getType(Reg).getSizeInBits();
-      }
-      MIRBuilder.buildSequence(Info.OrigRet.Regs[0], NewRegs, Indices);
-    }
   }
 
   CallSeqStart.addImm(Handler.getFrameSize())