fix sw_barrier

Author: sunjiweiswift

examples/09_gate_recurrent_unit/kernel_func.hpp

@@ -86,7 +86,7 @@ struct fused_config_t {
       {start_x_b, start_y_b});                                   \
   gemm_args.init(mem_desc_a, mem_desc_b, inner_loop_count_##id); \
   op(g, matAcc_##acc_id, gemm_args);                             \
-  SW_BARRIER();
+  sw_barrier();
 
 #define MATC_STORE(ptr_c)                                               \
   mem_desc_c.init(                                                      \
@@ -229,7 +229,7 @@ struct gru_layer {
         int start_n = (j)*wg_tile_n;
         CONFIG_SETTING(batch_size, -1, hidden_size);
         matAcc_0.init(0);
-        SW_BARRIER();
+        sw_barrier();
 
         // calculate reset gate: r_t = \sigmoid(X_t x W_ir + h_{t - 1} x W_hr)
         // acc0 = X_t x W_ir
@@ -278,19 +278,19 @@ struct gru_layer {
         matAcc_0.reg = matAcc_0.reg * (1 - matAcc_1.reg) +
             matAcc_1.reg *
                 xetla_cvt<Act_T, T, matAcc_t::tile_elems>(mat_hidden.reg);
-        SW_BARRIER();
+        sw_barrier();
 
         if (seq_id == seq_len - 1) {
           MATC_STORE(args->layer_output);
-          SW_BARRIER();
+          sw_barrier();
           __esimd_barrier();
         }
         MATC_STORE(args->cell_out_ptr + seq_id * io_size);
-        SW_BARRIER();
+        sw_barrier();
         __esimd_barrier();
 
         MATC_STORE(args->one_cell_ptr + (seq_id % 2) * io_size);
-        SW_BARRIER();
+        sw_barrier();
         __esimd_barrier();
       }
       args->hx_ptr = args->one_cell_ptr + (seq_id % 2) * io_size;
@@ -386,7 +386,7 @@ struct kernel_xcoder_gru_fusion {
     args.W_hz_ptr = (W_hz_ptr);
     args.W_in_ptr = (W_in_ptr);
     args.W_hn_ptr = (W_hn_ptr);
-    SW_BARRIER();
+    sw_barrier();
     fused_op::call(item, &args);
     ping = (ping + 1) % 2;
     pong = (pong + 1) % 2;
@@ -411,7 +411,7 @@ struct kernel_xcoder_gru_fusion {
           ? hidden_out_ptr
           : (ping_pong_buffer + ping * one_layer_size);
       args.layer_ptr = ((ping_pong_buffer + pong * one_layer_size));
-      SW_BARRIER();
+      sw_barrier();
       fused_op::call(item, &args);
       ping = (ping + 1) % 2;
       pong = (pong + 1) % 2;

include/common/core/barrier.hpp

@@ -26,6 +26,16 @@ namespace gpu::xetla {
 /// @addtogroup xetla_core_barrier
 /// @{
 
+/// sw_barrier, insert software scheduling barrier, for better code control
+///
+
+void sw_barrier() {
+#if __INTEL_LLVM_COMPILER >= 20250000
+#else
+  __ESIMD_NS::fence<__ESIMD_NS::fence_mask::sw_barrier>();
+#endif
+}
+
 /// @brief Initialize the number of named barrier index for a kernel.
 /// Available only on PVC. Only need to initialize once at the beginning.
 ///

tests/integration/mlp/int4/int4_mlp_gate_mul_up_fwd.hpp

@@ -188,7 +188,7 @@ class global_sum_reduce_two_mat_t {
           mat_zero, matAcc1_payload);
       subgroup::tile_store<cache_hint::uncached, cache_hint::write_back>(
           mat_zero, matAcc2_payload);
-      SW_BARRIER();
+      sw_barrier();
     }
   }
 };

tests/integration/vector_add/int32_1d/kernel_func.hpp

@@ -36,7 +36,7 @@ KERNEL_FUNC inline void vector_add_func(
   /// use block prefetch for b
   xetla_prefetch_global<dtype, SIMD, cache_hint::cached, cache_hint::cached>(
       b, offset);
-  SW_BARRIER();
+  sw_barrier();
   /// use scattered load for a
   xetla_vector<dtype, SIMD> ivector1 = xetla_load_global<
       dtype,

tests/integration/vector_add/tf32_1d/kernel_func.hpp

@@ -36,7 +36,7 @@ KERNEL_FUNC inline void vector_add_func(
   /// use block prefetch for b
   xetla_prefetch_global<dtype, SIMD, cache_hint::cached, cache_hint::cached>(
       b, offset);
-  SW_BARRIER();
+  sw_barrier();
   /// use scattered load for a
   xetla_vector<dtype, SIMD> ivector1 = xetla_load_global<
       dtype,

tests/unit/block_load_store/kernel_func.hpp

@@ -44,7 +44,7 @@ struct block_load_store_func {
         cache_hint::cached,
         cache_hint::cached,
         arch_tag>(src_tdesc);
-    SW_BARRIER();
+    sw_barrier();
     xetla_vector<dtype, bwidth* bheight> A_load_vec = xetla_tload_global<
         dtype,
         bwidth * bheight,

tests/unit/tile_load_store/kernel_func.hpp

@@ -242,7 +242,7 @@ struct tile_load_store_atomic_func {
     matBias.reg = matA.reg;
     matA.reg = 0;
     tile_store(matA, payload_store);
-    SW_BARRIER();
+    sw_barrier();
     tile_store(matBias, payload_store_add, check_tag);
   }
 };

tests/unit/tile_mma/kernel_func.hpp

@@ -103,9 +103,9 @@ struct tile_mma_func {
         matA, matA_payload);
     subgroup::tile_load<cache_hint::cached, cache_hint::cached>(
         matB, matB_payload);
-    SW_BARRIER();
+    sw_barrier();
     tile_mma::mma(matAcc, matAcc, matB, matA);
-    SW_BARRIER();
+    sw_barrier();
     matC.reg = xetla_cvt<dtypeC, dtypeAcc, matAcc_t::tile_desc::tile_elems>(
         matAcc.reg);
     matC_payload.init(c, n, m, n, 0, 0);