Merge from 'sycl' to 'sycl-web' (7 commits)

Author: iclsrc

clang/test/CodeGenSYCL/address-space-cond-op.cpp

@@ -11,6 +11,7 @@ struct S {
 // CHECK-NEXT:    [[LHS_ADDR:%.*]] = alloca ptr addrspace(4), align 8
 // CHECK-NEXT:    [[COND_ADDR_ASCAST:%.*]] = addrspacecast ptr [[COND_ADDR]] to ptr addrspace(4)
 // CHECK-NEXT:    [[LHS_ADDR_ASCAST:%.*]] = addrspacecast ptr [[LHS_ADDR]] to ptr addrspace(4)
+// CHECK-NEXT:    [[AGG_RESULT_ASCAST:%.*]] = addrspacecast ptr [[AGG_RESULT:%.*]] to ptr addrspace(4)
 // CHECK-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[COND:%.*]] to i8
 // CHECK-NEXT:    store i8 [[FROMBOOL]], ptr addrspace(4) [[COND_ADDR_ASCAST]], align 1
 // CHECK-NEXT:    store ptr addrspace(4) [[LHS:%.*]], ptr addrspace(4) [[LHS_ADDR_ASCAST]], align 8
@@ -25,7 +26,7 @@ struct S {
 // CHECK-NEXT:    br label [[COND_END]]
 // CHECK:       cond.end:
 // CHECK-NEXT:    [[COND_LVALUE:%.*]] = phi ptr addrspace(4) [ [[TMP1]], [[COND_TRUE]] ], [ [[RHS_ASCAST]], [[COND_FALSE]] ]
-// CHECK-NEXT:    call void @llvm.memcpy.p0.p4.i64(ptr align 2 [[AGG_RESULT:%.*]], ptr addrspace(4) align 2 [[COND_LVALUE]], i64 2, i1 false)
+// CHECK-NEXT:    call void @llvm.memcpy.p4.p4.i64(ptr addrspace(4) align 2 [[AGG_RESULT_ASCAST]], ptr addrspace(4) align 2 [[COND_LVALUE]], i64 2, i1 false)
 // CHECK-NEXT:    ret void
 //
 S foo(bool cond, S &lhs, S rhs) {

clang/test/CodeGenSYCL/nvptx-short-ptr.cpp

@@ -20,9 +20,9 @@
 
 // Targeting a 32-bit NVPTX, check that we see universal 32-bit pointers (the
 // option changes nothing)
-// CHECK32: target datalayout = "e-p:32:32-p6:32:32-p7:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+// CHECK32: target datalayout = "e-p:32:32-p6:32:32-p7:32:32-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64"
 
 // Targeting a 64-bit NVPTX target, check that we see 32-bit pointers for
 // shared (3), const (4), and local (5) address spaces only.
-// CHECK64-DEFAULT: target datalayout = "e-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
-// CHECK64-SHORT: target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+// CHECK64-DEFAULT: target datalayout = "e-p6:32:32-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64"
+// CHECK64-SHORT: target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64"

devops/dependencies-igc-dev.json

@@ -1,10 +1,10 @@
 {
   "linux": {
     "igc_dev": {
-      "github_tag": "igc-dev-5572ee3",
-      "version": "5572ee3",
-      "updated_at": "2025-09-28T11:41:20Z",
-      "url": "https://api.github.com/repos/intel/intel-graphics-compiler/actions/artifacts/4125423999/zip",
+      "github_tag": "igc-dev-e146785",
+      "version": "e146785",
+      "updated_at": "2025-10-02T03:05:40Z",
+      "url": "https://api.github.com/repos/intel/intel-graphics-compiler/actions/artifacts/4161218080/zip",
       "root": "{DEPS_ROOT}/opencl/runtime/linux/oclgpu"
     }
   }

llvm-spirv/include/LLVMSPIRVExtensions.inc

@@ -80,3 +80,4 @@ EXT(SPV_INTEL_bfloat16_arithmetic)
 EXT(SPV_INTEL_ternary_bitwise_function)
 EXT(SPV_INTEL_int4)
 EXT(SPV_INTEL_function_variants)
+EXT(SPV_INTEL_shader_atomic_bfloat16)

llvm-spirv/include/LLVMSPIRVOpts.h

@@ -273,14 +273,14 @@ class TranslatorOpts {
   }
 
   void setFnVarFeatures(std::vector<uint32_t> Features) noexcept {
-    FnVarFeatures = Features;
+    FnVarFeatures = std::move(Features);
   }
   std::vector<uint32_t> getFnVarFeatures() const noexcept {
     return FnVarFeatures;
   }
 
   void setFnVarCapabilities(std::vector<uint32_t> Capabilities) noexcept {
-    FnVarCapabilities = Capabilities;
+    FnVarCapabilities = std::move(Capabilities);
   }
   std::vector<uint32_t> getFnVarCapabilities() const noexcept {
     return FnVarCapabilities;
@@ -289,7 +289,9 @@ class TranslatorOpts {
   void setFnVarSpecEnable(bool Val) noexcept { FnVarSpecEnable = Val; }
   bool getFnVarSpecEnable() const noexcept { return FnVarSpecEnable; }
 
-  void setFnVarSpvOut(std::string Val) noexcept { FnVarSpvOut = Val; }
+  void setFnVarSpvOut(std::string Val) noexcept {
+    FnVarSpvOut = std::move(Val);
+  }
   std::string getFnVarSpvOut() const noexcept { return FnVarSpvOut; }
 
   // Check that options passed to --fnvar-xxx flags make sense. Return true on

llvm-spirv/lib/SPIRV/LLVMToSPIRVDbgTran.cpp

@@ -1310,13 +1310,14 @@ SPIRVEntry *LLVMToSPIRVDbgTran::transDbgFunction(const DISubprogram *Func) {
     if (DISubprogram *FuncDecl = Func->getDeclaration())
       Ops.push_back(transDbgEntry(FuncDecl)->getId());
     else {
-      Ops.push_back(getDebugInfoNoneId());
       if (BM->getDebugInfoEIS() == SPIRVEIS_NonSemantic_Shader_DebugInfo_200) {
         // Translate targetFuncName mostly for Fortran trampoline function if it
         // is the case
         StringRef TargetFunc = Func->getTargetFuncName();
-        if (!TargetFunc.empty())
+        if (!TargetFunc.empty()) {
+          Ops.push_back(getDebugInfoNoneId());
           Ops.push_back(BM->getString(TargetFunc.str())->getId());
+        }
       }
     }
 

llvm-spirv/lib/SPIRV/Mangler/ManglingUtils.cpp

@@ -93,6 +93,7 @@ static const char *PrimitiveNames[PRIMITIVE_NUM] = {
     "intel_sub_group_avc_ime_result_dual_reference_streamin_t"
 };
 
+// clang-format off
 const char *MangledTypes[PRIMITIVE_NUM] = {
     "b",                                 // BOOL
     "h",                                 // UCHAR
@@ -106,7 +107,7 @@ const char *MangledTypes[PRIMITIVE_NUM] = {
     "Dh",                                // HALF
     "f",                                 // FLOAT
     "d",                                 // DOUBLE
-    "u6__bf16",                          // __BF16
+    "DF16b",                             // __BF16
     "v",                                 // VOID
     "z",                                 // VarArg
     "14ocl_image1d_ro",                  // PRIMITIVE_IMAGE1D_RO_T
@@ -175,6 +176,7 @@ const char *MangledTypes[PRIMITIVE_NUM] = {
     "55ocl_intel_sub_group_avc_ime_single_reference_streamin_t",          // PRIMITIVE_SUB_GROUP_AVC_IME_SINGLE_REF_STREAMIN_T
     "53ocl_intel_sub_group_avc_ime_dual_reference_streamin_t"             // PRIMITIVE_SUB_GROUP_AVC_IME_DUAL_REF_STREAMIN_T
 };
+// clang-format on
 
 const char *ReadableAttribute[ATTR_NUM] = {
     "restrict", "volatile",   "const",   "__private",

llvm-spirv/lib/SPIRV/SPIRVRegularizeLLVM.cpp

@@ -421,6 +421,42 @@ void SPIRVRegularizeLLVMBase::cleanupConversionToNonStdIntegers(Module *M) {
   }
 }
 
+void SPIRVRegularizeLLVMBase::replacePrivateConstGlobalsWithAllocas(Module *M) {
+  SmallVector<GlobalVariable *> GlobalsToRemove;
+  for (auto &GV : M->globals()) {
+
+    if (!GV.isConstant() || !GV.hasInternalLinkage() ||
+        !(GV.getAddressSpace() == SPIRAS_Private) || !GV.hasInitializer() ||
+        GV.getName().starts_with("llvm.compiler.used") ||
+        GV.getName().starts_with("llvm.used"))
+      continue;
+
+    SmallVector<User *> Users(GV.users());
+    // TODO: Handle other llvm::User types, for example, constant expressions.
+    if (llvm::any_of(Users, [](User *U) { return !isa<Instruction>(U); }))
+      continue;
+
+    DenseMap<Function *, AllocaInst *> LocalCopies;
+    for (User *U : Users) {
+      Instruction *Inst = cast<Instruction>(U);
+      Function *F = Inst->getFunction();
+      AllocaInst *&AI = LocalCopies[F];
+      if (!AI) {
+        IRBuilder<> Builder(&*F->getEntryBlock().getFirstInsertionPt());
+        AI = Builder.CreateAlloca(GV.getValueType(), nullptr, GV.getName());
+        if (GV.getAlign())
+          AI->setAlignment(GV.getAlign().value());
+        Builder.CreateStore(GV.getInitializer(), AI);
+      }
+      Inst->replaceUsesOfWith(&GV, AI);
+    }
+    GlobalsToRemove.push_back(&GV);
+  }
+
+  for (GlobalVariable *GV : GlobalsToRemove)
+    GV->eraseFromParent();
+}
+
 bool SPIRVRegularizeLLVMBase::runRegularizeLLVM(Module &Module) {
   M = &Module;
   Ctx = &M->getContext();
@@ -582,6 +618,7 @@ bool SPIRVRegularizeLLVMBase::regularize() {
   addKernelEntryPoint(M);
   expandSYCLTypeUsing(M);
   cleanupConversionToNonStdIntegers(M);
+  replacePrivateConstGlobalsWithAllocas(M);
 
   // Kernels called by other kernels
   std::vector<Function *> CalledKernels;

llvm-spirv/lib/SPIRV/SPIRVRegularizeLLVM.h

@@ -102,6 +102,11 @@ class SPIRVRegularizeLLVMBase {
   // non-standard integer types.
   void cleanupConversionToNonStdIntegers(llvm::Module *M);
 
+  // Move internal constants in the private address space to function-scope
+  // variables. Such globals would otherwise be translated with Function storage
+  // class which is invalid for global variables in SPIR-V.
+  void replacePrivateConstGlobalsWithAllocas(llvm::Module *M);
+
   // According to the specification, the operands of a shift instruction must be
   // a scalar/vector of integer. When LLVM-IR contains a shift instruction with
   // i1 operands, they are treated as a bool. We need to extend them to i32 to

llvm-spirv/lib/SPIRV/SPIRVUtil.cpp

@@ -528,8 +528,8 @@ ParamType lastFuncParamType(StringRef MangledName) {
   char Mangled = Copy.back();
   std::string Mangled2 = Copy.substr(Copy.size() - 2);
 
-  std::string Mangled6 = Copy.substr(Copy.size() - 6);
-  if (Mangled6 == "__bf16") {
+  std::string Mangled5 = Copy.substr(Copy.size() - 5);
+  if (Mangled5 == "DF16b") {
     return ParamType::FLOAT;
   }