@@ -110,21 +110,6 @@ define amdgpu_ps i32 @abs32(i32 inreg %val0) {
110110 ret i32 %zext
111111}
112112
113- define amdgpu_ps i32 @absdiff32 (i32 inreg %val0 , i32 inreg %val1 ) {
114- ; CHECK-LABEL: absdiff32:
115- ; CHECK: ; %bb.0:
116- ; CHECK-NEXT: s_absdiff_i32 s0, s0, s1
117- ; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
118- ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
119- ; CHECK-NEXT: v_readfirstlane_b32 s0, v0
120- ; CHECK-NEXT: ; return to shader part epilog
121- %diff = sub i32 %val0 , %val1
122- %result = call i32 @llvm.abs.i32 (i32 %diff , i1 false )
123- %cmp = icmp ne i32 %result , 0
124- %zext = zext i1 %cmp to i32
125- ret i32 %zext
126- }
127-
128113define amdgpu_ps i32 @and32 (i32 inreg %val0 , i32 inreg %val1 ) {
129114; CHECK-LABEL: and32:
130115; CHECK: ; %bb.0:
@@ -623,14 +608,14 @@ define amdgpu_ps i32 @si_pc_add_rel_offset_must_not_optimize() {
623608; CHECK-NEXT: s_add_u32 s0, s0, __unnamed_1@rel32@lo+4
624609; CHECK-NEXT: s_addc_u32 s1, s1, __unnamed_1@rel32@hi+12
625610; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
626- ; CHECK-NEXT: s_cbranch_scc0 .LBB36_2
611+ ; CHECK-NEXT: s_cbranch_scc0 .LBB35_2
627612; CHECK-NEXT: ; %bb.1: ; %endif
628613; CHECK-NEXT: s_mov_b32 s0, 1
629- ; CHECK-NEXT: s_branch .LBB36_3
630- ; CHECK-NEXT: .LBB36_2 : ; %if
614+ ; CHECK-NEXT: s_branch .LBB35_3
615+ ; CHECK-NEXT: .LBB35_2 : ; %if
631616; CHECK-NEXT: s_mov_b32 s0, 0
632- ; CHECK-NEXT: s_branch .LBB36_3
633- ; CHECK-NEXT: .LBB36_3 :
617+ ; CHECK-NEXT: s_branch .LBB35_3
618+ ; CHECK-NEXT: .LBB35_3 :
634619 %cmp = icmp ne ptr addrspace (4 ) @1 , null
635620 br i1 %cmp , label %endif , label %if
636621
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