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1 parent 1cd4105 commit 12afc8dCopy full SHA for 12afc8d
third_party/intel/lib/TritonIntelGPUTransforms/AccelerateMatmul.cpp
@@ -119,11 +119,6 @@ class BlockedToDPAS : public OpRewritePattern<tt::DotOp> {
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unsigned opsPerChan =
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ttg::intel::DpasEncodingAttr::getOpsPerChannel(elemType);
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- // We are upcasting FP8 to FP16
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- if (oldAType.getElementType().isFloat8E5M2() ||
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- oldAType.getElementType().isFloat8E4M3FN())
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- dpasElemBitWidths = 2 * dpasElemBitWidths;
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-
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SmallVector<unsigned> order = {1, 0}; // TODO: acceptable default arg?
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llvm::errs() << "a: " << a << "\n";
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Operation *aOp = a.getDefiningOp();
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