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rmadayikigcbot
rmadayik
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igcbot
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Enable staged compilation for wave intrinsics CS/PS via AIL for Starfield
Add global and PSO input AILs to enable staged compilation for wave intrinsics CS/PS. Global flags will enable the feature for the app and the PSO input reverse AIL flags will be used to disable staged compilation for problematic shaders.
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5 files changed

+29
-17
lines changed

5 files changed

+29
-17
lines changed

‎IGC/AdaptorCommon/API/igc.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,8 @@ typedef enum CG_FLAG_t {
154154
ValidStage2Modes(prev_ctx_ptr, stats) \
155155
)
156156

157+
#define FastestS1Options(ctx_ptr) (IGC_GET_FLAG_VALUE(FastestS1Experiments) ? IGC_GET_FLAG_VALUE(FastestS1Experiments) : ctx_ptr->getModuleMetaData()->compOpt.FastestS1Options)
158+
157159
// CodePatch compilation experimental flags
158160
typedef enum
159161
{
@@ -181,6 +183,12 @@ typedef enum
181183
FCEXP_QUICKTOKEN_ALLOC = ( 0x1 << 0xa ),
182184
FCEXP_DISABLE_UNROLL = ( 0x1 << 0xb ),
183185
FCEXP_TOBE_DESIGNED = ( 0x1 << 0xc ),
186+
187+
// Current default stage 1 options. *Must* be updated whenever the default changes.
188+
FCEXP_DEFAULT = ( FCEXP_DISABLE_LVN | FCEXP_LINEARSCAN | FCEXP_DISABLE_GOPT | FCEXP_LOCAL_SCHEDULING | FCEXP_PRERA_SCHEDULING | FCEXP_SPILL_COMPRESSION | FCEXP_QUICKTOKEN_ALLOC ),
189+
190+
// Alias for UMD to indicate staged compilation must be disabled
191+
FCEXP_DISABLED = FCEXP_TOBE_DESIGNED
184192
} FCEXP_FLAG_t;
185193

186194
#endif // __IGC_H

‎IGC/Compiler/CISACodeGen/CISABuilder.cpp‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4996,7 +4996,7 @@ namespace IGC
49964996
IGC_GET_FLAG_VALUE(ForceFastestSIMD)) &&
49974997
m_program->m_DriverInfo->SupportFastestStage1())
49984998
{
4999-
if (IGC_GET_FLAG_VALUE(FastestS1Experiments) == FCEXP_NO_EXPRIMENT)
4999+
if (FastestS1Options(context) == FCEXP_NO_EXPRIMENT)
50005000
{
50015001
SaveOption(vISA_LocalScheduling, false);
50025002
SaveOption(vISA_preRA_Schedule, false);
@@ -5011,32 +5011,32 @@ namespace IGC
50115011
}
50125012
else
50135013
{
5014-
if (IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_FASTSPILL)
5014+
if (FastestS1Options(context) & FCEXP_FASTSPILL)
50155015
SaveOption(vISA_FastSpill, true);
50165016

5017-
if (IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_LOCAL_SCHEDULING)
5017+
if (FastestS1Options(context) & FCEXP_LOCAL_SCHEDULING)
50185018
SaveOption(vISA_LocalScheduling, false);
50195019

5020-
if (IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_PRERA_SCHEDULING)
5020+
if (FastestS1Options(context) & FCEXP_PRERA_SCHEDULING)
50215021
SaveOption(vISA_preRA_Schedule, false);
50225022

5023-
if (IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_NO_REMAT)
5023+
if (FastestS1Options(context) & FCEXP_NO_REMAT)
50245024
SaveOption(vISA_NoRemat, true);
50255025

5026-
if (IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_SPILL_COMPRESSION)
5026+
if (FastestS1Options(context) & FCEXP_SPILL_COMPRESSION)
50275027
SaveOption(vISA_SpillSpaceCompression, false);
50285028

5029-
if (IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_LOCAL_DECL_SPLIT_GLOBAL_RA)
5029+
if (FastestS1Options(context) & FCEXP_LOCAL_DECL_SPLIT_GLOBAL_RA)
50305030
SaveOption(vISA_LocalDeclareSplitInGlobalRA, false);
50315031

5032-
if (IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_DISABLE_LVN)
5032+
if (FastestS1Options(context) & FCEXP_DISABLE_LVN)
50335033
SaveOption(vISA_LVN, false);
5034-
if (IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_QUICKTOKEN_ALLOC)
5034+
if (FastestS1Options(context) & FCEXP_QUICKTOKEN_ALLOC)
50355035
SaveOption(vISA_QuickTokenAllocation, true);
5036-
if (IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_LINEARSCAN)
5036+
if (FastestS1Options(context) & FCEXP_LINEARSCAN)
50375037
SaveOption(vISA_LinearScan, true); // use linearScan
50385038

5039-
if (IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_1PASSRA)
5039+
if (FastestS1Options(context) & FCEXP_1PASSRA)
50405040
SaveOption(vISA_FastCompileRA, true); // use 1 iteration RA
50415041
}
50425042
}

‎IGC/Compiler/CISACodeGen/ShaderCodeGen.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1382,8 +1382,8 @@ void OptimizeIR(CodeGenContext* const pContext)
13821382

13831383
bool disableGOPT = ( (IsStage1FastestCompile(pContext->m_CgFlag, pContext->m_StagingCtx) ||
13841384
IGC_GET_FLAG_VALUE(ForceFastestSIMD)) &&
1385-
((IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_DISABLE_GOPT) ||
1386-
IGC_GET_FLAG_VALUE(FastestS1Experiments) == FCEXP_NO_EXPRIMENT ||
1385+
((FastestS1Options(pContext) & FCEXP_DISABLE_GOPT) ||
1386+
FastestS1Options(pContext) == FCEXP_NO_EXPRIMENT ||
13871387
pContext->getModuleMetaData()->compOpt.DisableFastestGopt));
13881388

13891389
if (pContext->m_instrTypes.hasMultipleBB && !disableGOPT)
@@ -1447,8 +1447,8 @@ void OptimizeIR(CodeGenContext* const pContext)
14471447
bool hasIndexTemp = (pContext->m_indexableTempSize[0] > 0);
14481448
bool disableLoopUnrollStage1 =
14491449
IsStage1FastestCompile(pContext->m_CgFlag, pContext->m_StagingCtx) &&
1450-
(IGC_GET_FLAG_VALUE(FastestS1Experiments) == FCEXP_NO_EXPRIMENT ||
1451-
(IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_DISABLE_UNROLL));
1450+
(FastestS1Options(pContext) == FCEXP_NO_EXPRIMENT ||
1451+
(FastestS1Options(pContext) & FCEXP_DISABLE_UNROLL));
14521452
if ((LoopUnrollThreshold > 0 &&
14531453
unroll &&
14541454
!disableLoopUnrollStage1)
@@ -1643,8 +1643,8 @@ void OptimizeIR(CodeGenContext* const pContext)
16431643
// Enable loop unrolling for stage 1 for now due to persisting regressions
16441644
bool disableLoopUnrollStage1 =
16451645
IsStage1FastestCompile(pContext->m_CgFlag, pContext->m_StagingCtx) &&
1646-
(//IGC_GET_FLAG_VALUE(FastestS1Experiments) == FCEXP_NO_EXPRIMENT ||
1647-
(IGC_GET_FLAG_VALUE(FastestS1Experiments) & FCEXP_DISABLE_UNROLL));
1646+
(//FastestS1Options(pContext) == FCEXP_NO_EXPRIMENT ||
1647+
(FastestS1Options(pContext) & FCEXP_DISABLE_UNROLL));
16481648
if ((LoopUnrollThreshold > 0 &&
16491649
unroll &&
16501650
!disableLoopUnrollStage1)

‎IGC/common/MDFrameWork.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -443,6 +443,8 @@ namespace IGC
443443
bool DisableFDivToFMulInvOpt = false;
444444
bool initializePhiSampleSourceWA = false;
445445
bool WaDisableSubspanUseNoMaskForCB = false;
446+
447+
unsigned FastestS1Options = 0; // FCEXP_NO_EXPRIMENT. Can't access the enum here for some reason.
446448
};
447449

448450
enum class ThreadIDLayout

‎IGC/common/igc_flags.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -665,6 +665,8 @@ DECLARE_IGC_REGKEY(bool, DisableFastestLinearScan, false, "Disable Linear
665665
DECLARE_IGC_REGKEY(bool, DisableFastestGopt, false, "Disable global optimizations for stage 1 shaders.", false)
666666
DECLARE_IGC_REGKEY(bool, ForceFastestSIMD, false, "Force pixel shader to return SIMD8 as fast as possible.", false)
667667
DECLARE_IGC_REGKEY(bool, EnableFastestSingleCSSIMD, true, "Enable selecting single CS SIMD in staged compilation.", false)
668+
DECLARE_IGC_REGKEY(bool, EnableFastestForAllWaveIntrinsicsCS, false, "Enable staged compilation for all CS that use wave intrinsics.", false)
669+
DECLARE_IGC_REGKEY(bool, EnableFastestForAllWaveIntrinsicsPS, false, "Enable staged compilation for all PS that use wave intrinsics.", false)
668670
DECLARE_IGC_REGKEY(bool, ForceBestSIMD, false, "Force pixel shader to return the best SIMD, either SIMD16 or SIMD8.", false)
669671
DECLARE_IGC_REGKEY(bool, SkipTREarlyExitCheck, false, "Skip SIMD16 early exit check in ShaderCodeGen", false)
670672
DECLARE_IGC_REGKEY(bool, EnableTCSHWBarriers, false, "Enable TCS pass with HW barriers support. Default TCS pass is TCS pass with multiple continuation functions.", false)

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