Improve DF math translation and

rematerilization.

Improvements to reduce register pressure:
Reduce temp dcl size created for DF math translation.
Extend RA rematerilization to handle source with acc mod.

Author: kychendev

visa/Rematerialization.cpp

@@ -530,9 +530,9 @@ namespace vISA
             (G4_RegFileKind::G4_GRF | G4_RegFileKind::G4_INPUT)) == 0x0)
             return false;
 
-        // Skip remat if src opnd uses special acc registers
-        if (src->getAccRegSel() != ACC_UNDEFINED)
-            return false;
+        G4_AccRegSel accRegSel = src->getAccRegSel();
+        if (accRegSel != ACC_UNDEFINED && accRegSel != NOACC)
+          return false;
 
         // Lookup defs of src in program
         auto opIt = operations.find(topdcl);
@@ -1242,6 +1242,11 @@ namespace vISA
                                     rematSrc = createSrcRgn(src->asSrcRegRegion(), uniqueDef->first->getDst(),
                                         (*prevRematIt).second.first->getDst()->getTopDcl());
 
+                                    if (src->asSrcRegRegion()->getAccRegSel() == NOACC)
+                                    {
+                                      rematSrc->setAccRegSel(NOACC);
+                                    }
+
                                     reduceNumUses(src->getTopDcl());
 
 #if 0
@@ -1262,6 +1267,12 @@ namespace vISA
                                 std::list<G4_INST*> newInsts;
                                 G4_INST* cacheInst = nullptr;
                                 rematSrc = rematerialize(src->asSrcRegRegion(), bb, uniqueDef, newInsts, cacheInst);
+
+                                if (src->asSrcRegRegion()->getAccRegSel() == NOACC)
+                                {
+                                  rematSrc->setAccRegSel(NOACC);
+                                }
+
                                 while (!newInsts.empty())
                                 {
                                     bb->insertBefore(instIt, newInsts.front());

visa/VisaToG4/TranslateMath.cpp

@@ -238,8 +238,8 @@ int IR_Builder::translateVISAArithmeticDoubleInst(
     G4_Declare *t13 = createTempVarWithNoSpill(element_size, Type_DF, Any);
 
     // r0 = 0.0:df, r1 = 1.0:df
-    G4_Declare *t0  = getImmDcl(dbl_constant_0, element_size);
-    G4_Declare *t1  = getImmDcl(dbl_constant_1, element_size);
+    G4_Declare* t0 = getImmDcl(dbl_constant_0, exsize);
+    G4_Declare* t1 = getImmDcl(dbl_constant_1, exsize);
 
     inst = createPseudoKills({ t6, t7, t8, t9, t10, t11, t12, t13, tmpFlag }, PseudoKillType::Src);
 
@@ -1281,10 +1281,10 @@ int IR_Builder::translateVISAArithmeticDoubleSQRTInst(
 
 
     // temp registers
-    G4_Declare *t0 = getImmDcl(createDFImm(0.0), element_size);
-    G4_Declare *t1 = getImmDcl(createDFImm(1.0), element_size);
-    G4_Declare *t2 = getImmDcl(createDFImm(0.5), element_size);
-    G4_Declare* t3 = getImmDcl(createDFImm(1.5), element_size);
+    G4_Declare *t0 = getImmDcl(createDFImm(0.0), exsize);
+    G4_Declare *t1 = getImmDcl(createDFImm(1.0), exsize);
+    G4_Declare *t2 = getImmDcl(createDFImm(0.5), exsize);
+    G4_Declare *t3 = getImmDcl(createDFImm(1.5), exsize);
     G4_Declare *t6  = createTempVarWithNoSpill(element_size, Type_DF, Any);
     G4_Declare *t7  = createTempVarWithNoSpill(element_size, Type_DF, Any);
     G4_Declare *t8  = createTempVarWithNoSpill(element_size, Type_DF, Any);