Add xe_hpg common tests

Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>

Author: BartoszDunajski

shared/test/common/helpers/CMakeLists.txt

@@ -44,6 +44,12 @@ if(TESTS_XEHP_AND_LATER)
   )
 endif()
 
+if(TESTS_DG2_AND_LATER)
+  list(APPEND NEO_CORE_HELPERS_TESTS
+       ${CMAKE_CURRENT_SOURCE_DIR}/hw_helper_tests_dg2_and_later.cpp
+  )
+endif()
+
 add_subdirectories()
 
 target_sources(${TARGET_NAME} PRIVATE

shared/test/common/helpers/hw_helper_tests_dg2_and_later.cpp

@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/helpers/hw_helper.h"
+#include "shared/test/common/fixtures/device_fixture.h"
+
+#include "test.h"
+
+using namespace NEO;
+
+using HwHelperDg2AndLaterTest = Test<DeviceFixture>;
+
+HWTEST2_F(HwHelperDg2AndLaterTest, GivenUseL1CacheAsTrueWhenCallSetL1CachePolicyThenL1CachePolicyL1CacheControlIsSetProperly, IsAtLeastXeHpgCore) {
+    using RENDER_SURFACE_STATE = typename FamilyType::RENDER_SURFACE_STATE;
+    using SURFACE_TYPE = typename RENDER_SURFACE_STATE::SURFACE_TYPE;
+
+    auto &helper = reinterpret_cast<HwHelperHw<FamilyType> &>(HwHelperHw<FamilyType>::get());
+
+    RENDER_SURFACE_STATE surfaceState = FamilyType::cmdInitRenderSurfaceState;
+    bool useL1Cache = true;
+    helper.setL1CachePolicy(useL1Cache, &surfaceState, defaultHwInfo.get());
+    EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB, surfaceState.getL1CachePolicyL1CacheControl());
+}
+HWTEST2_F(HwHelperDg2AndLaterTest, GivenUseL1CacheAsFalseWhenCallSetL1CachePolicyThenL1CachePolicyL1CacheControlIsNotSet, IsAtLeastXeHpgCore) {
+    using RENDER_SURFACE_STATE = typename FamilyType::RENDER_SURFACE_STATE;
+    using SURFACE_TYPE = typename RENDER_SURFACE_STATE::SURFACE_TYPE;
+
+    auto &helper = reinterpret_cast<HwHelperHw<FamilyType> &>(HwHelperHw<FamilyType>::get());
+    RENDER_SURFACE_STATE surfaceState = FamilyType::cmdInitRenderSurfaceState;
+    bool useL1Cache = false;
+    helper.setL1CachePolicy(useL1Cache, &surfaceState, defaultHwInfo.get());
+    EXPECT_NE(RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB, surfaceState.getL1CachePolicyL1CacheControl());
+}

shared/test/common/helpers/includes/test_traits_common.h

@@ -11,3 +11,4 @@
 #include "shared/test/common/gen8/test_traits_gen8.h"
 #include "shared/test/common/gen9/test_traits_gen9.h"
 #include "shared/test/common/xe_hp_core/test_traits_xe_hp_core.h"
+#include "shared/test/common/xe_hpg_core/test_traits_xe_hpg_core.h"

shared/test/common/libult/xe_hpg_core.cpp

@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/helpers/populate_factory.h"
+#include "shared/test/common/libult/ult_command_stream_receiver.h"
+
+namespace NEO {
+
+typedef XE_HPG_COREFamily Family;
+
+static auto gfxCore = IGFX_XE_HPG_CORE;
+
+extern CommandStreamReceiverCreateFunc commandStreamReceiverFactory[2 * IGFX_MAX_CORE];
+
+template <>
+void populateFactoryTable<UltCommandStreamReceiver<Family>>() {
+    commandStreamReceiverFactory[IGFX_MAX_CORE + gfxCore] = UltCommandStreamReceiver<Family>::create;
+}
+
+struct enableXeHpgCore {
+    enableXeHpgCore() {
+        populateFactoryTable<UltCommandStreamReceiver<Family>>();
+    }
+};
+
+static enableXeHpgCore enable;
+
+template class UltCommandStreamReceiver<XE_HPG_COREFamily>;
+} // namespace NEO

shared/test/common/test_configuration/aub_tests/xe_hpg_core/CMakeLists.txt

@@ -0,0 +1,15 @@
+#
+# Copyright (C) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: MIT
+#
+
+if(TESTS_XE_HPG_CORE)
+  set(NEO_SHARED_aub_tests_configurations
+      ${NEO_SHARED_aub_tests_configurations}
+      ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/aub_tests_configuration_xe_hpg_core.cpp
+  )
+
+  set(NEO_SHARED_aub_tests_configurations ${NEO_SHARED_aub_tests_configurations} PARENT_SCOPE)
+endif()

shared/test/common/test_configuration/aub_tests/xe_hpg_core/aub_tests_configuration_xe_hpg_core.cpp

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/test/common/test_configuration/aub_tests/aub_tests_configuration.h"
+
+#include "hw_cmds.h"
+
+using namespace NEO;
+
+template <>
+AubTestsConfig GetAubTestsConfig<XE_HPG_COREFamily>() {
+    AubTestsConfig aubTestsConfig;
+    aubTestsConfig.testCanonicalAddress = true;
+    return aubTestsConfig;
+}

shared/test/common/xe_hpg_core/CMakeLists.txt

@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: MIT
+#
+
+if(TESTS_XE_HPG_CORE)
+
+  set(NEO_CORE_TESTS_XE_HPG_CORE
+      ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/simd_helper_tests_xe_hpg_core.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/test_traits_xe_hpg_core.h
+  )
+  set_property(GLOBAL PROPERTY NEO_CORE_TESTS_XE_HPG_CORE ${NEO_CORE_TESTS_XE_HPG_CORE})
+  add_subdirectories()
+
+  set(IGDRCL_SRCS_tests_xe_hpg_core_excludes
+      ${CMAKE_CURRENT_SOURCE_DIR}/excludes_xe_hpg_core.cpp
+  )
+  set_property(GLOBAL APPEND PROPERTY IGDRCL_SRCS_tests_excludes ${IGDRCL_SRCS_tests_xe_hpg_core_excludes})
+
+  target_sources(${TARGET_NAME} PRIVATE
+                 ${IGDRCL_SRCS_tests_xe_hpg_core_excludes}
+                 ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+                 ${CMAKE_CURRENT_SOURCE_DIR}/image_surface_state_tests_xe_hpg_core.cpp
+                 ${CMAKE_CURRENT_SOURCE_DIR}/test_preemption_xe_hpg_core.cpp
+                 ${COMPUTE_RUNTIME_ULT_XE_HPG_CORE}
+  )
+
+endif()

shared/test/common/xe_hpg_core/cmd_parse_xe_hpg_core.cpp

@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/xe_hpg_core/hw_cmds.h"
+using GenStruct = NEO::XE_HPG_CORE;
+using GenGfxFamily = NEO::XE_HPG_COREFamily;
+#include "shared/test/common/cmd_parse/cmd_parse_xehp_and_later.inl"

shared/test/common/xe_hpg_core/dg2/CMakeLists.txt

@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: MIT
+#
+
+if(TESTS_DG2)
+  set(IGDRCL_SRCS_tests_xe_hpg_core_dg2_excludes
+      ${CMAKE_CURRENT_SOURCE_DIR}/excludes_dg2.cpp
+  )
+  set_property(GLOBAL APPEND PROPERTY IGDRCL_SRCS_tests_excludes ${IGDRCL_SRCS_tests_xe_hpg_core_dg2_excludes})
+
+  set(NEO_CORE_TESTS_XE_HPG_CORE_DG2
+      ${IGDRCL_SRCS_tests_xe_hpg_core_dg2_excludes}
+      ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/test_encode_dispatch_kernel_dg2.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/test_hw_info_config_dg2.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/test_hw_helper_dg2.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/test_encode_dg2.cpp
+  )
+
+  target_sources(${TARGET_NAME} PRIVATE ${NEO_CORE_TESTS_XE_HPG_CORE_DG2})
+endif()

shared/test/common/xe_hpg_core/dg2/excludes_dg2.cpp

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "test.h"
+
+HWTEST_EXCLUDE_PRODUCT(CommandEncodeStatesTest, givenSlmTotalSizeEqualZeroWhenDispatchingKernelThenSharedMemorySizeIsSetCorrectly, IGFX_DG2);