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raiyanlaCompute-Runtime-Automation
raiyanla
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Compute-Runtime-Automation
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Add L3_CONTROL cmd format for Gen12LP
Change-Id: Ibae6c3f10a54accb333aa1b21163024aac8cf93c Signed-off-by: Raiyan Latif <raiyan.latif@intel.com>
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‎shared/source/gen12lp/command_stream_receiver_hw_gen12lp.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -223,6 +223,8 @@ const Family::GPGPU_CSR_BASE_ADDRESS Family::cmdInitGpgpuCsrBaseAddress = Family
223223
const Family::STATE_SIP Family::cmdInitStateSip = Family::STATE_SIP::sInit();
224224
const Family::BINDING_TABLE_STATE Family::cmdInitBindingTableState = Family::BINDING_TABLE_STATE::sInit();
225225
const Family::MI_USER_INTERRUPT Family::cmdInitUserInterrupt = Family::MI_USER_INTERRUPT::sInit();
226+
const Family::L3_CONTROL Family::cmdInitL3ControlWithoutPostSync = Family::L3_CONTROL::sInit();
227+
const Family::L3_CONTROL Family::cmdInitL3ControlWithPostSync = Family::L3_CONTROL::sInit();
226228
const Family::XY_COPY_BLT Family::cmdInitXyCopyBlt = Family::XY_COPY_BLT::sInit();
227229
const Family::MI_FLUSH_DW Family::cmdInitMiFlushDw = Family::MI_FLUSH_DW::sInit();
228230
const Family::XY_FAST_COLOR_BLT Family::cmdInitXyColorBlt = Family::XY_FAST_COLOR_BLT::sInit();

‎shared/source/gen12lp/hw_cmds_base.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,8 @@ struct TGLLPFamily : public GEN12LP {
8484
static const STATE_SIP cmdInitStateSip;
8585
static const BINDING_TABLE_STATE cmdInitBindingTableState;
8686
static const MI_USER_INTERRUPT cmdInitUserInterrupt;
87+
static const L3_CONTROL cmdInitL3ControlWithoutPostSync;
88+
static const L3_CONTROL cmdInitL3ControlWithPostSync;
8789
static const XY_COPY_BLT cmdInitXyCopyBlt;
8890
static const MI_FLUSH_DW cmdInitMiFlushDw;
8991
static const XY_FAST_COLOR_BLT cmdInitXyColorBlt;

‎shared/source/generated/gen12lp/hw_cmds_generated_gen12lp.inl‎

Lines changed: 351 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5223,6 +5223,357 @@ typedef struct tagGPGPU_CSR_BASE_ADDRESS {
52235223
} GPGPU_CSR_BASE_ADDRESS;
52245224
STATIC_ASSERT(12 == sizeof(GPGPU_CSR_BASE_ADDRESS));
52255225

5226+
typedef struct tagL3_FLUSH_ADDRESS_RANGE {
5227+
union tagTheStructure {
5228+
struct tagCommon {
5229+
uint64_t Reserved_0 : BITFIELD_RANGE(0, 2);
5230+
uint64_t AddressMask : BITFIELD_RANGE(3, 8);
5231+
uint64_t Reserved_9 : BITFIELD_RANGE(9, 11);
5232+
uint64_t AddressLow : BITFIELD_RANGE(12, 31);
5233+
uint64_t AddressHigh : BITFIELD_RANGE(32, 47);
5234+
uint64_t Reserved_48 : BITFIELD_RANGE(48, 59);
5235+
uint64_t L3FlushEvictionPolicy : BITFIELD_RANGE(60, 61);
5236+
uint64_t Reserved_62 : BITFIELD_RANGE(62, 63);
5237+
} Common;
5238+
struct tagCommonA0Stepping {
5239+
uint64_t AddressHigh : BITFIELD_RANGE(0, 15);
5240+
uint64_t Reserved_0 : BITFIELD_RANGE(16, 27);
5241+
uint64_t L3FlushEvictionPolicy : BITFIELD_RANGE(28, 29);
5242+
uint64_t Reserved_9 : BITFIELD_RANGE(30, 34);
5243+
uint64_t AddressMask : BITFIELD_RANGE(35, 40);
5244+
uint64_t Reserved_48 : BITFIELD_RANGE(41, 43);
5245+
uint64_t AddressLow : BITFIELD_RANGE(44, 63);
5246+
} CommonA0Stepping;
5247+
uint32_t RawData[2];
5248+
} TheStructure;
5249+
5250+
typedef enum tagL3_FLUSH_EVICTION_POLICY {
5251+
L3_FLUSH_EVICTION_POLICY_FLUSH_L3_WITH_EVICTION = 0x0,
5252+
} L3_FLUSH_EVICTION_POLICY;
5253+
inline void init() {
5254+
memset(&TheStructure, 0, sizeof(TheStructure));
5255+
}
5256+
static tagL3_FLUSH_ADDRESS_RANGE sInit() {
5257+
L3_FLUSH_ADDRESS_RANGE state;
5258+
state.init();
5259+
return state;
5260+
}
5261+
inline uint32_t &getRawData(const uint32_t index) {
5262+
UNRECOVERABLE_IF(index >= 2);
5263+
return TheStructure.RawData[index];
5264+
}
5265+
5266+
typedef enum tagADDRESSLOW {
5267+
ADDRESSLOW_BIT_SHIFT = 0xC,
5268+
ADDRESSLOW_ALIGN_SIZE = 0x1000,
5269+
} ADDRESSLOW;
5270+
5271+
inline void setAddressLow(const uint64_t value, bool isA0Stepping) {
5272+
if (isA0Stepping) {
5273+
TheStructure.CommonA0Stepping.AddressLow = value >> ADDRESSLOW_BIT_SHIFT;
5274+
} else {
5275+
TheStructure.Common.AddressLow = value >> ADDRESSLOW_BIT_SHIFT;
5276+
}
5277+
}
5278+
5279+
inline uint64_t getAddressLow(bool isA0Stepping) const {
5280+
if (isA0Stepping) {
5281+
return (TheStructure.CommonA0Stepping.AddressLow << ADDRESSLOW_BIT_SHIFT) & uint64_t(0xffffffff);
5282+
} else {
5283+
return (TheStructure.Common.AddressLow << ADDRESSLOW_BIT_SHIFT);
5284+
}
5285+
}
5286+
5287+
inline void setAddressHigh(const uint64_t value, bool isA0Stepping) {
5288+
if (isA0Stepping) {
5289+
TheStructure.CommonA0Stepping.AddressHigh = value;
5290+
} else {
5291+
TheStructure.Common.AddressHigh = value;
5292+
}
5293+
}
5294+
5295+
inline uint64_t getAddressHigh(bool isA0Stepping) const {
5296+
if (isA0Stepping) {
5297+
return (TheStructure.CommonA0Stepping.AddressHigh);
5298+
} else {
5299+
return (TheStructure.Common.AddressHigh);
5300+
}
5301+
}
5302+
5303+
inline void setAddress(const uint64_t value, bool isA0Stepping) {
5304+
setAddressLow(static_cast<uint32_t>(value), isA0Stepping);
5305+
setAddressHigh(static_cast<uint32_t>(value >> 32), isA0Stepping);
5306+
}
5307+
5308+
inline uint64_t getAddress(bool isA0Stepping) const {
5309+
return static_cast<uint64_t>(getAddressLow(isA0Stepping)) | (static_cast<uint64_t>(getAddressHigh(isA0Stepping)) << 32);
5310+
}
5311+
5312+
inline void setL3FlushEvictionPolicy(const L3_FLUSH_EVICTION_POLICY value, bool isA0Stepping) {
5313+
if (isA0Stepping) {
5314+
TheStructure.CommonA0Stepping.L3FlushEvictionPolicy = value;
5315+
} else {
5316+
TheStructure.Common.L3FlushEvictionPolicy = value;
5317+
}
5318+
}
5319+
inline L3_FLUSH_EVICTION_POLICY getL3FlushEvictionPolicy(bool isA0Stepping) const {
5320+
if (isA0Stepping) {
5321+
return static_cast<L3_FLUSH_EVICTION_POLICY>(TheStructure.CommonA0Stepping.L3FlushEvictionPolicy);
5322+
} else {
5323+
return static_cast<L3_FLUSH_EVICTION_POLICY>(TheStructure.Common.L3FlushEvictionPolicy);
5324+
}
5325+
}
5326+
inline void setAddressMask(const uint64_t value, bool isA0Stepping) {
5327+
if (isA0Stepping) {
5328+
TheStructure.CommonA0Stepping.AddressMask = value;
5329+
} else {
5330+
UNRECOVERABLE_IF(value > 0x1f8);
5331+
TheStructure.Common.AddressMask = value;
5332+
}
5333+
}
5334+
inline uint32_t getAddressMask(bool isA0Stepping) const {
5335+
if (isA0Stepping) {
5336+
return TheStructure.CommonA0Stepping.AddressMask;
5337+
} else {
5338+
return TheStructure.Common.AddressMask;
5339+
}
5340+
}
5341+
} L3_FLUSH_ADDRESS_RANGE;
5342+
STATIC_ASSERT(8 == sizeof(L3_FLUSH_ADDRESS_RANGE));
5343+
5344+
struct L3_CONTROL_BASE {
5345+
union tagTheStructure {
5346+
struct tagCommon {
5347+
uint32_t Length : BITFIELD_RANGE(0, 7);
5348+
uint32_t DepthCacheFlush : BITFIELD_RANGE(8, 8);
5349+
uint32_t RenderTargetCacheFlushEnable : BITFIELD_RANGE(9, 9);
5350+
uint32_t HdcPipelineFlush : BITFIELD_RANGE(10, 10);
5351+
uint32_t Reserved_11 : BITFIELD_RANGE(11, 13);
5352+
uint32_t PostSyncOperation : BITFIELD_RANGE(14, 14);
5353+
uint32_t PostSyncOperationL3CacheabilityControl : BITFIELD_RANGE(15, 15); // removed on DG1
5354+
uint32_t Reserved_16 : BITFIELD_RANGE(16, 19);
5355+
uint32_t CommandStreamerStallEnable : BITFIELD_RANGE(20, 20);
5356+
uint32_t DestinationAddressType : BITFIELD_RANGE(21, 21);
5357+
uint32_t Reserved_22 : BITFIELD_RANGE(22, 22);
5358+
uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(23, 23);
5359+
uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26);
5360+
uint32_t CommandSubtype : BITFIELD_RANGE(27, 28);
5361+
uint32_t Type : BITFIELD_RANGE(29, 31);
5362+
} Common;
5363+
uint32_t RawData[1];
5364+
} TheStructure;
5365+
5366+
typedef enum tagLENGTH {
5367+
LENGTH_POST_SYNC_OPERATION_DISABLED = 1,
5368+
LENGTH_POST_SYNC_OPERATION_ENABLED = 5,
5369+
} LENGTH;
5370+
typedef enum tagPOST_SYNC_OPERATION {
5371+
POST_SYNC_OPERATION_NO_WRITE = 0x0,
5372+
POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA = 0x1,
5373+
} POST_SYNC_OPERATION;
5374+
typedef enum tagPOST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL {
5375+
POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL_DEFAULT_MOCS = 0x0,
5376+
POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL_CACHEABLE_MOCS = 0x1,
5377+
} POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL;
5378+
typedef enum tagDESTINATION_ADDRESS_TYPE {
5379+
DESTINATION_ADDRESS_TYPE_PPGTT = 0x0,
5380+
DESTINATION_ADDRESS_TYPE_GGTT = 0x1,
5381+
} DESTINATION_ADDRESS_TYPE;
5382+
typedef enum tag_3D_COMMAND_SUB_OPCODE {
5383+
_3D_COMMAND_SUB_OPCODE_L3_CONTROL = 0x1,
5384+
} _3D_COMMAND_SUB_OPCODE;
5385+
typedef enum tag_3D_COMMAND_OPCODE {
5386+
_3D_COMMAND_OPCODE_L3_CONTROL = 0x5,
5387+
} _3D_COMMAND_OPCODE;
5388+
typedef enum tagCOMMAND_SUBTYPE {
5389+
COMMAND_SUBTYPE_GFXPIPE_3D = 0x3,
5390+
} COMMAND_SUBTYPE;
5391+
typedef enum tagTYPE {
5392+
TYPE_GFXPIPE = 0x3,
5393+
} TYPE;
5394+
inline void init(void) {
5395+
memset(&TheStructure, 0, sizeof(TheStructure));
5396+
TheStructure.Common.PostSyncOperation = POST_SYNC_OPERATION_NO_WRITE;
5397+
TheStructure.Common.PostSyncOperationL3CacheabilityControl = POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL_DEFAULT_MOCS;
5398+
TheStructure.Common.DestinationAddressType = DESTINATION_ADDRESS_TYPE_PPGTT;
5399+
TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_L3_CONTROL;
5400+
TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_L3_CONTROL;
5401+
TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_3D;
5402+
TheStructure.Common.Type = TYPE_GFXPIPE;
5403+
}
5404+
static L3_CONTROL_BASE sInit(void) {
5405+
L3_CONTROL_BASE state;
5406+
state.init();
5407+
return state;
5408+
}
5409+
inline uint32_t &getRawData(const uint32_t index) {
5410+
UNRECOVERABLE_IF(index >= 7);
5411+
return TheStructure.RawData[index];
5412+
}
5413+
inline void setLength(const LENGTH value) {
5414+
TheStructure.Common.Length = value;
5415+
}
5416+
inline LENGTH getLength(void) const {
5417+
return (LENGTH)TheStructure.Common.Length;
5418+
}
5419+
inline void setDepthCacheFlush(const bool value) {
5420+
TheStructure.Common.DepthCacheFlush = value;
5421+
}
5422+
inline bool getDepthCacheFlush(void) const {
5423+
return TheStructure.Common.DepthCacheFlush;
5424+
}
5425+
inline void setRenderTargetCacheFlushEnable(const bool value) {
5426+
TheStructure.Common.RenderTargetCacheFlushEnable = value;
5427+
}
5428+
inline bool getRenderTargetCacheFlushEnable(void) const {
5429+
return TheStructure.Common.RenderTargetCacheFlushEnable;
5430+
}
5431+
inline void setHdcPipelineFlush(const bool value) {
5432+
TheStructure.Common.HdcPipelineFlush = value;
5433+
}
5434+
inline bool getHdcPipelineFlush(void) const {
5435+
return TheStructure.Common.HdcPipelineFlush;
5436+
}
5437+
inline void setPostSyncOperation(const POST_SYNC_OPERATION value) {
5438+
TheStructure.Common.PostSyncOperation = value;
5439+
}
5440+
inline POST_SYNC_OPERATION getPostSyncOperation(void) const {
5441+
return static_cast<POST_SYNC_OPERATION>(TheStructure.Common.PostSyncOperation);
5442+
}
5443+
inline void setPostSyncOperationL3CacheabilityControl(const POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL value) {
5444+
TheStructure.Common.PostSyncOperationL3CacheabilityControl = value;
5445+
}
5446+
inline POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL getPostSyncOperationL3CacheabilityControl(void) const {
5447+
return static_cast<POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL>(TheStructure.Common.PostSyncOperationL3CacheabilityControl);
5448+
}
5449+
inline void setCommandStreamerStallEnable(const bool value) {
5450+
TheStructure.Common.CommandStreamerStallEnable = value;
5451+
}
5452+
inline bool getCommandStreamerStallEnable(void) const {
5453+
return TheStructure.Common.CommandStreamerStallEnable;
5454+
}
5455+
inline void setDestinationAddressType(const DESTINATION_ADDRESS_TYPE value) {
5456+
TheStructure.Common.DestinationAddressType = value;
5457+
}
5458+
inline DESTINATION_ADDRESS_TYPE getDestinationAddressType(void) const {
5459+
return static_cast<DESTINATION_ADDRESS_TYPE>(TheStructure.Common.DestinationAddressType);
5460+
}
5461+
inline void setType(const TYPE value) {
5462+
TheStructure.Common.Type = value;
5463+
}
5464+
inline TYPE getType(void) const {
5465+
return static_cast<TYPE>(TheStructure.Common.Type);
5466+
}
5467+
};
5468+
5469+
struct L3_CONTROL_POST_SYNC_DATA {
5470+
union tagTheStructure {
5471+
struct tagCommon {
5472+
uint64_t Reserved_96 : BITFIELD_RANGE(0, 2);
5473+
uint64_t Address : BITFIELD_RANGE(3, 47);
5474+
uint64_t Reserved_144 : BITFIELD_RANGE(48, 63);
5475+
uint64_t ImmediateData;
5476+
} Common;
5477+
uint32_t RawData[4];
5478+
} TheStructure;
5479+
5480+
inline void init(void) {
5481+
memset(&TheStructure, 0, sizeof(TheStructure));
5482+
}
5483+
5484+
typedef enum tagADDRESS {
5485+
ADDRESS_BIT_SHIFT = 0x3,
5486+
ADDRESS_ALIGN_SIZE = 0x8,
5487+
} ADDRESS;
5488+
inline void setAddress(const uint64_t value) {
5489+
UNRECOVERABLE_IF(value > 0xfffffffffff8L);
5490+
TheStructure.Common.Address = value >> ADDRESS_BIT_SHIFT;
5491+
}
5492+
inline uint64_t getAddress(void) const {
5493+
return TheStructure.Common.Address << ADDRESS_BIT_SHIFT;
5494+
}
5495+
inline void setImmediateData(const uint64_t value) {
5496+
TheStructure.Common.ImmediateData = value;
5497+
}
5498+
inline uint64_t getImmediateData(void) const {
5499+
return TheStructure.Common.ImmediateData;
5500+
}
5501+
};
5502+
5503+
struct L3_CONTROL {
5504+
union tagTheStructure {
5505+
struct tagCommon {
5506+
L3_CONTROL_BASE Base;
5507+
L3_CONTROL_POST_SYNC_DATA PostSyncData;
5508+
L3_FLUSH_ADDRESS_RANGE L3FlushAddressRange;
5509+
} Common;
5510+
uint32_t RawData[7];
5511+
} TheStructure;
5512+
5513+
inline void init(void) {
5514+
memset(&TheStructure, 0, sizeof(TheStructure));
5515+
getBase().init();
5516+
getPostSyncData().init();
5517+
getBase().setLength(L3_CONTROL_BASE::LENGTH_POST_SYNC_OPERATION_ENABLED);
5518+
TheStructure.Common.L3FlushAddressRange.init();
5519+
}
5520+
5521+
inline void setL3FlushAddressRange(const L3_FLUSH_ADDRESS_RANGE &value) {
5522+
TheStructure.Common.L3FlushAddressRange = value;
5523+
}
5524+
inline L3_FLUSH_ADDRESS_RANGE &getL3FlushAddressRange(void) {
5525+
return TheStructure.Common.L3FlushAddressRange;
5526+
}
5527+
inline const L3_FLUSH_ADDRESS_RANGE &getL3FlushAddressRange(void) const {
5528+
return TheStructure.Common.L3FlushAddressRange;
5529+
}
5530+
5531+
static L3_CONTROL sInit(void) {
5532+
L3_CONTROL state;
5533+
state.init();
5534+
return state;
5535+
}
5536+
inline uint32_t &getRawData(const uint32_t index) {
5537+
UNRECOVERABLE_IF(index >= 7);
5538+
return TheStructure.RawData[index];
5539+
}
5540+
5541+
L3_CONTROL_BASE &getBase() {
5542+
return TheStructure.Common.Base;
5543+
}
5544+
5545+
const L3_CONTROL_BASE &getBase() const {
5546+
return TheStructure.Common.Base;
5547+
}
5548+
5549+
L3_CONTROL_POST_SYNC_DATA &getPostSyncData() {
5550+
return TheStructure.Common.PostSyncData;
5551+
}
5552+
5553+
const L3_CONTROL_POST_SYNC_DATA &getPostSyncData() const {
5554+
return TheStructure.Common.PostSyncData;
5555+
}
5556+
5557+
inline void setPostSyncAddress(const uint64_t value) {
5558+
getPostSyncData().setAddress(value);
5559+
}
5560+
5561+
inline uint64_t getPostSyncAddress(void) const {
5562+
return getPostSyncData().getAddress();
5563+
}
5564+
5565+
inline void setPostSyncImmediateData(const uint64_t value) {
5566+
getPostSyncData().setImmediateData(value);
5567+
}
5568+
5569+
inline uint64_t getPostSyncImmediateData(void) const {
5570+
return getPostSyncData().getImmediateData();
5571+
}
5572+
};
5573+
5574+
STATIC_ASSERT(28 == sizeof(L3_CONTROL));
5575+
STATIC_ASSERT(std::is_pod<L3_CONTROL>::value);
5576+
52265577
typedef struct tagXY_BLOCK_COPY_BLT {
52275578
union tagTheStructure {
52285579
struct tagCommon {

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