Initial DG2 support

Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>

Author: BartoszDunajski

cmake/fill_gens.cmake

@@ -9,4 +9,6 @@ list(APPEND ALL_GEN_TYPES "GEN9")
 list(APPEND ALL_GEN_TYPES "GEN11")
 list(APPEND ALL_GEN_TYPES "GEN12LP")
 list(APPEND ALL_GEN_TYPES "XE_HP_CORE")
-list(APPEND XEHP_AND_LATER_GENS "XE_HP_CORE")
+list(APPEND ALL_GEN_TYPES "XE_HPG_CORE")
+list(APPEND XEHP_AND_LATER_GENS "XE_HP_CORE" "XE_HPG_CORE")
+list(APPEND DG2_AND_LATER_GENS "XE_HPG_CORE")

cmake/setup_platform_flags.cmake

@@ -25,6 +25,15 @@ foreach(GEN_TYPE ${DEVICE_ENQUEUE_DISABLED_GENS})
   set(SUPPORT_DEVICE_ENQUEUE_${GEN_TYPE} FALSE CACHE BOOL "Disabled support ${GEN_TYPE} for device side enqueue" FORCE)
 endforeach()
 
+foreach(GEN_TYPE ${DG2_AND_LATER_GENS})
+  if(TESTS_${GEN_TYPE})
+    set(TESTS_DG2_AND_LATER 1)
+  endif()
+  if(SUPPORT_${GEN_TYPE})
+    set(SUPPORT_DG2_AND_LATER 1)
+  endif()
+endforeach()
+
 # Add supported and tested platforms
 if(SUPPORT_GEN8)
   set(CORE_GEN8_REVISIONS 0)
@@ -234,3 +243,21 @@ if(SUPPORT_XE_HP_CORE)
     endif()
   endif()
 endif()
+
+if(SUPPORT_XE_HPG_CORE)
+  set(CORE_XE_HPG_CORE_REVISIONS 0)
+  if(TESTS_XE_HPG_CORE)
+    ADD_ITEM_FOR_GEN("FAMILY_NAME" "TESTED" "XE_HPG_CORE" "XE_HPG_COREFamily")
+  endif()
+  if(SUPPORT_DG2)
+    set(DG2_XE_HPG_CORE_REVISIONS 0)
+    ADD_PRODUCT("SUPPORTED" "DG2" "IGFX_DG2")
+    ADD_PLATFORM_FOR_GEN("SUPPORTED" "XE_HPG_CORE" "DG2" "DG2")
+    ADD_PLATFORM_FOR_GEN("SUPPORTED_AUX_TRANSLATION" "XE_HPG_CORE" "DG2" "DG2")
+    ADD_PLATFORM_FOR_GEN("SUPPORTED_IMAGES" "XE_HPG_CORE" "DG2" "DG2")
+    if(TESTS_DG2)
+      ADD_ITEM_FOR_GEN("PLATFORMS" "TESTED" "XE_HPG_CORE" "DG2")
+      ADD_PRODUCT("TESTED" "DG2" "IGFX_DG2")
+    endif()
+  endif()
+endif()

level_zero/core/source/xe_hpg_core/CMakeLists.txt

@@ -0,0 +1,21 @@
+#
+# Copyright (C) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: MIT
+#
+
+if(SUPPORT_XE_HPG_CORE)
+  set(HW_SOURCES_XE_HPG_CORE
+      ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/debugger_xe_hpg_core.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/image_xe_hpg_core.inl
+      ${CMAKE_CURRENT_SOURCE_DIR}/sampler_xe_hpg_core.inl
+      ${CMAKE_CURRENT_SOURCE_DIR}/enable_family_full_l0_xe_hpg_core.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/l0_hw_helper_xe_hpg_core.cpp
+  )
+
+  add_subdirectories()
+
+  target_sources(${L0_STATIC_LIB_NAME} PRIVATE ${HW_SOURCES_XE_HPG_CORE})
+  set_property(GLOBAL PROPERTY L0_HW_SOURCES_XE_HPG_CORE ${HW_SOURCES_XE_HPG_CORE})
+endif()

level_zero/core/source/xe_hpg_core/debugger_xe_hpg_core.cpp

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/debugger/debugger_l0.inl"
+
+namespace NEO {
+struct XE_HPG_COREFamily;
+using GfxFamily = XE_HPG_COREFamily;
+
+} // namespace NEO
+
+namespace L0 {
+template class DebuggerL0Hw<NEO::GfxFamily>;
+DebuggerL0PopulateFactory<IGFX_XE_HPG_CORE, NEO::GfxFamily> debuggerXeHpgCore;
+} // namespace L0

level_zero/core/source/xe_hpg_core/dg2/CMakeLists.txt

@@ -0,0 +1,19 @@
+#
+# Copyright (C) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: MIT
+#
+
+if(SUPPORT_DG2)
+  set(HW_SOURCES_XE_HPG_CORE
+      ${HW_SOURCES_XE_HPG_CORE}
+      ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_dg2.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_dg2.h
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdqueue_dg2.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/kernel_dg2.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/image_dg2.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/sampler_dg2.cpp
+      PARENT_SCOPE
+  )
+endif()

level_zero/core/source/xe_hpg_core/dg2/cmdlist_dg2.cpp

@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "cmdlist_dg2.h"
+
+#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_xehp_and_later.inl"
+
+#include "cmdlist_extended.inl"
+
+namespace L0 {
+
+template struct CommandListCoreFamily<IGFX_XE_HPG_CORE>;
+
+static CommandListPopulateFactory<IGFX_DG2, CommandListProductFamily<IGFX_DG2>>
+    populateDG2;
+
+static CommandListImmediatePopulateFactory<IGFX_DG2, CommandListImmediateProductFamily<IGFX_DG2>>
+    populateDG2Immediate;
+
+} // namespace L0

level_zero/core/source/xe_hpg_core/dg2/cmdlist_dg2.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/cmdlist/cmdlist_hw.h"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.h"
+
+namespace L0 {
+template <>
+struct CommandListImmediateProductFamily<IGFX_DG2> : public CommandListCoreFamilyImmediate<IGFX_XE_HPG_CORE> {
+    using CommandListCoreFamilyImmediate::CommandListCoreFamilyImmediate;
+};
+template <>
+struct CommandListProductFamily<IGFX_DG2> : public CommandListCoreFamily<IGFX_XE_HPG_CORE> {
+    using CommandListCoreFamily::CommandListCoreFamily;
+    void clearComputeModePropertiesIfNeeded(bool requiresCoherency, uint32_t numGrfRequired, uint32_t threadArbitrationPolicy) override {
+        finalStreamState.stateComputeMode = {};
+        finalStreamState.stateComputeMode.setProperties(requiresCoherency, numGrfRequired, threadArbitrationPolicy);
+    }
+};
+
+} // namespace L0

level_zero/core/source/xe_hpg_core/dg2/cmdqueue_dg2.cpp

@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/xe_hpg_core/hw_cmds.h"
+#include "shared/source/xe_hpg_core/hw_info.h"
+
+#include "level_zero/core/source/cmdqueue/cmdqueue_hw.inl"
+#include "level_zero/core/source/cmdqueue/cmdqueue_xe_hp_core_and_later.inl"
+
+#include "cmdqueue_extended.inl"
+
+namespace L0 {
+template struct CommandQueueHw<IGFX_XE_HPG_CORE>;
+static CommandQueuePopulateFactory<IGFX_DG2, CommandQueueHw<IGFX_XE_HPG_CORE>>
+    populateDG2;
+
+} // namespace L0

level_zero/core/source/xe_hpg_core/dg2/image_dg2.cpp

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/xe_hpg_core/image_xe_hpg_core.inl"
+
+namespace L0 {
+
+template <>
+struct ImageProductFamily<IGFX_DG2> : public ImageCoreFamily<IGFX_XE_HPG_CORE> {
+    using ImageCoreFamily::ImageCoreFamily;
+
+    ze_result_t initialize(Device *device, const ze_image_desc_t *desc) override {
+        return ImageCoreFamily<IGFX_XE_HPG_CORE>::initialize(device, desc);
+    };
+};
+
+static ImagePopulateFactory<IGFX_DG2, ImageProductFamily<IGFX_DG2>> populateDG2;
+
+} // namespace L0

level_zero/core/source/xe_hpg_core/dg2/kernel_dg2.cpp

@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/kernel/kernel_hw.h"
+
+namespace L0 {
+
+static KernelPopulateFactory<IGFX_DG2, KernelHw<IGFX_XE_HPG_CORE>> populateDG2;
+
+} // namespace L0