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zzdanowiczCompute-Runtime-Automation
zzdanowicz
authored and
Compute-Runtime-Automation
committed
Add HW commands const definitions
Change-Id: If2e9d7f7f707b7b8c7bd8dbd3853ab3b6dad0c9a
1 parent 0c2f5aa commit 158f200

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48 files changed

+371
-154
lines changed

‎runtime/command_queue/gpgpu_walker.inl‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -39,14 +39,14 @@ void GpgpuWalkerHelper<GfxFamily>::addAluReadModifyWriteRegister(
3939
typedef typename GfxFamily::MI_MATH MI_MATH;
4040
typedef typename GfxFamily::MI_MATH_ALU_INST_INLINE MI_MATH_ALU_INST_INLINE;
4141
auto pCmd = reinterpret_cast<MI_LOAD_REGISTER_REG *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_REG)));
42-
*pCmd = MI_LOAD_REGISTER_REG::sInit();
42+
*pCmd = GfxFamily::cmdInitLoadRegisterReg;
4343
pCmd->setSourceRegisterAddress(aluRegister);
4444
pCmd->setDestinationRegisterAddress(CS_GPR_R0);
4545

4646
// Load "Mask" into CS_GPR_R1
4747
typedef typename GfxFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
4848
auto pCmd2 = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM)));
49-
*pCmd2 = MI_LOAD_REGISTER_IMM::sInit();
49+
*pCmd2 = GfxFamily::cmdInitLoadRegisterImm;
5050
pCmd2->setRegisterOffset(CS_GPR_R1);
5151
pCmd2->setDataDword(mask);
5252

@@ -85,13 +85,13 @@ void GpgpuWalkerHelper<GfxFamily>::addAluReadModifyWriteRegister(
8585

8686
// LOAD value of CS_GPR_R0 into "Register"
8787
auto pCmd4 = reinterpret_cast<MI_LOAD_REGISTER_REG *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_REG)));
88-
*pCmd4 = MI_LOAD_REGISTER_REG::sInit();
88+
*pCmd4 = GfxFamily::cmdInitLoadRegisterReg;
8989
pCmd4->setSourceRegisterAddress(CS_GPR_R0);
9090
pCmd4->setDestinationRegisterAddress(aluRegister);
9191

9292
// Add PIPE_CONTROL to flush caches
9393
auto pCmd5 = reinterpret_cast<PIPE_CONTROL *>(pCommandStream->getSpace(sizeof(PIPE_CONTROL)));
94-
*pCmd5 = PIPE_CONTROL::sInit();
94+
*pCmd5 = GfxFamily::cmdInitPipeControl;
9595
pCmd5->setCommandStreamerStallEnable(true);
9696
pCmd5->setDcFlushEnable(true);
9797
pCmd5->setTextureCacheInvalidationEnable(true);
@@ -115,7 +115,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchProfilingCommandsStart(
115115

116116
//low part
117117
auto pMICmdLow = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
118-
*pMICmdLow = MI_STORE_REGISTER_MEM::sInit();
118+
*pMICmdLow = GfxFamily::cmdInitStoreRegisterMem;
119119
adjustMiStoreRegMemMode(pMICmdLow);
120120
pMICmdLow->setRegisterAddress(GP_THREAD_TIME_REG_ADDRESS_OFFSET_LOW);
121121
pMICmdLow->setMemoryAddress(TimeStampAddress);
@@ -130,15 +130,15 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchProfilingCommandsEnd(
130130

131131
// PIPE_CONTROL for global timestamp
132132
auto pPipeControlCmd = (PIPE_CONTROL *)commandStream->getSpace(sizeof(PIPE_CONTROL));
133-
*pPipeControlCmd = PIPE_CONTROL::sInit();
133+
*pPipeControlCmd = GfxFamily::cmdInitPipeControl;
134134
pPipeControlCmd->setCommandStreamerStallEnable(true);
135135

136136
//MI_STORE_REGISTER_MEM for context local timestamp
137137
uint64_t TimeStampAddress = hwTimeStamps.getGraphicsAllocation()->getGpuAddress() + ptrDiff(&hwTimeStamps.tag->ContextEndTS, hwTimeStamps.getGraphicsAllocation()->getUnderlyingBuffer());
138138

139139
//low part
140140
auto pMICmdLow = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
141-
*pMICmdLow = MI_STORE_REGISTER_MEM::sInit();
141+
*pMICmdLow = GfxFamily::cmdInitStoreRegisterMem;
142142
adjustMiStoreRegMemMode(pMICmdLow);
143143
pMICmdLow->setRegisterAddress(GP_THREAD_TIME_REG_ADDRESS_OFFSET_LOW);
144144
pMICmdLow->setMemoryAddress(TimeStampAddress);
@@ -157,7 +157,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersNoopidRegisterCommands(
157157
: reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.DMAFenceIdEnd));
158158

159159
auto pNoopIdRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
160-
*pNoopIdRegister = MI_STORE_REGISTER_MEM::sInit();
160+
*pNoopIdRegister = GfxFamily::cmdInitStoreRegisterMem;
161161
pNoopIdRegister->setRegisterAddress(OCLRT::INSTR_MMIO_NOOPID);
162162
pNoopIdRegister->setMemoryAddress(address);
163163
}
@@ -175,7 +175,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersReadFreqRegisterCommands(
175175
: reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.CoreFreqEnd));
176176

177177
auto pCoreFreqRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
178-
*pCoreFreqRegister = MI_STORE_REGISTER_MEM::sInit();
178+
*pCoreFreqRegister = GfxFamily::cmdInitStoreRegisterMem;
179179
pCoreFreqRegister->setRegisterAddress(OCLRT::INSTR_MMIO_RPSTAT1);
180180
pCoreFreqRegister->setMemoryAddress(address);
181181
}
@@ -195,7 +195,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersGeneralPurposeCounterComm
195195
// Read General Purpose counters
196196
for (uint16_t i = 0; i < OCLRT::INSTR_GENERAL_PURPOSE_COUNTERS_COUNT; i++) {
197197
auto pGeneralPurposeRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
198-
*pGeneralPurposeRegister = MI_STORE_REGISTER_MEM::sInit();
198+
*pGeneralPurposeRegister = GfxFamily::cmdInitStoreRegisterMem;
199199
uint32_t regAddr = INSTR_GFX_OFFSETS::INSTR_PERF_CNT_1_DW0 + i * sizeof(cl_uint);
200200
pGeneralPurposeRegister->setRegisterAddress(regAddr);
201201
//Gp field is 2*uint64 wide so it can hold 4 uint32
@@ -223,7 +223,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersUserCounterCommands(
223223

224224
for (uint32_t i = 0; i < userRegs->RegsCount; i++) {
225225
auto pRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
226-
*pRegister = MI_STORE_REGISTER_MEM::sInit();
226+
*pRegister = GfxFamily::cmdInitStoreRegisterMem;
227227

228228
regAddr = userRegs->Reg[i].Offset;
229229
pRegister->setRegisterAddress(regAddr);
@@ -234,7 +234,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersUserCounterCommands(
234234

235235
if (userRegs->Reg[i].BitSize > 32) {
236236
pRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
237-
*pRegister = MI_STORE_REGISTER_MEM::sInit();
237+
*pRegister = GfxFamily::cmdInitStoreRegisterMem;
238238

239239
regAddr += sizeof(cl_uint);
240240
pRegister->setRegisterAddress(regAddr);
@@ -256,21 +256,21 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersOABufferStateCommands(
256256
uint64_t address = 0;
257257
//OA Status
258258
auto pOaRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
259-
*pOaRegister = MI_STORE_REGISTER_MEM::sInit();
259+
*pOaRegister = GfxFamily::cmdInitStoreRegisterMem;
260260
pOaRegister->setRegisterAddress(INSTR_GFX_OFFSETS::INSTR_OA_STATUS);
261261
address = reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.OaStatus));
262262
pOaRegister->setMemoryAddress(address);
263263

264264
//OA Head
265265
pOaRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
266-
*pOaRegister = MI_STORE_REGISTER_MEM::sInit();
266+
*pOaRegister = GfxFamily::cmdInitStoreRegisterMem;
267267
pOaRegister->setRegisterAddress(INSTR_GFX_OFFSETS::INSTR_OA_HEAD_PTR);
268268
address = reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.OaHead));
269269
pOaRegister->setMemoryAddress(address);
270270

271271
//OA Tail
272272
pOaRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
273-
*pOaRegister = MI_STORE_REGISTER_MEM::sInit();
273+
*pOaRegister = GfxFamily::cmdInitStoreRegisterMem;
274274
pOaRegister->setRegisterAddress(INSTR_GFX_OFFSETS::INSTR_OA_TAIL_PTR);
275275
address = reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.OaTail));
276276
pOaRegister->setMemoryAddress(address);
@@ -291,7 +291,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersCommandsStart(
291291
uint64_t address = 0;
292292
//flush command streamer
293293
auto pPipeControlCmd = (PIPE_CONTROL *)commandStream->getSpace(sizeof(PIPE_CONTROL));
294-
*pPipeControlCmd = PIPE_CONTROL::sInit();
294+
*pPipeControlCmd = GfxFamily::cmdInitPipeControl;
295295
pPipeControlCmd->setCommandStreamerStallEnable(true);
296296

297297
//Store value of NOOPID register
@@ -303,7 +303,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersCommandsStart(
303303
GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersGeneralPurposeCounterCommands(commandQueue, hwPerfCounter, commandStream, true);
304304

305305
auto pReportPerfCount = (MI_REPORT_PERF_COUNT *)commandStream->getSpace(sizeof(MI_REPORT_PERF_COUNT));
306-
*pReportPerfCount = MI_REPORT_PERF_COUNT::sInit();
306+
*pReportPerfCount = GfxFamily::cmdInitReportPerfCount;
307307
pReportPerfCount->setReportId(currentReportId);
308308
address = reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.HwPerfReportBegin.Oa));
309309
pReportPerfCount->setMemoryAddress(address);
@@ -333,7 +333,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersCommandsEnd(
333333

334334
//flush command streamer
335335
auto pPipeControlCmd = (PIPE_CONTROL *)commandStream->getSpace(sizeof(PIPE_CONTROL));
336-
*pPipeControlCmd = PIPE_CONTROL::sInit();
336+
*pPipeControlCmd = GfxFamily::cmdInitPipeControl;
337337
pPipeControlCmd->setCommandStreamerStallEnable(true);
338338

339339
GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersOABufferStateCommands(commandQueue, hwPerfCounter, commandStream);
@@ -343,7 +343,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersCommandsEnd(
343343
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(commandStream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, address, 0llu);
344344

345345
auto pReportPerfCount = (MI_REPORT_PERF_COUNT *)commandStream->getSpace(sizeof(MI_REPORT_PERF_COUNT));
346-
*pReportPerfCount = MI_REPORT_PERF_COUNT::sInit();
346+
*pReportPerfCount = GfxFamily::cmdInitReportPerfCount;
347347
pReportPerfCount->setReportId(currentReportId);
348348
address = reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.HwPerfReportEnd.Oa));
349349
pReportPerfCount->setMemoryAddress(address);

‎runtime/command_queue/gpgpu_walker_base.inl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -165,7 +165,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchScheduler(
165165

166166
// Add BB Start Cmd to the SLB in the Primary Batch Buffer
167167
auto *bbStart = (MI_BATCH_BUFFER_START *)commandStream->getSpace(sizeof(MI_BATCH_BUFFER_START));
168-
*bbStart = MI_BATCH_BUFFER_START::sInit();
168+
*bbStart = GfxFamily::cmdInitBatchBufferStart;
169169
bbStart->setSecondLevelBatchBuffer(MI_BATCH_BUFFER_START::SECOND_LEVEL_BATCH_BUFFER_FIRST_LEVEL_BATCH);
170170
uint64_t slbAddress = devQueueHw.getSlbBuffer()->getGpuAddress();
171171
bbStart->setBatchBufferStartAddressGraphicsaddress472(slbAddress);

‎runtime/command_stream/aub_command_stream_receiver_hw.inl‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -478,15 +478,15 @@ void AUBCommandStreamReceiverHw<GfxFamily>::submitBatchBuffer(size_t engineIndex
478478
pTail = engineInfo.pRingBuffer;
479479
} else if (engineInfo.tailRingBuffer == 0) {
480480
// Add a LRI if this is our first submission
481-
auto lri = MI_LOAD_REGISTER_IMM::sInit();
481+
auto lri = GfxFamily::cmdInitLoadRegisterImm;
482482
lri.setRegisterOffset(AubMemDump::computeRegisterOffset(csTraits.mmioBase, 0x2244));
483483
lri.setDataDword(0x00010000);
484484
*(MI_LOAD_REGISTER_IMM *)pTail = lri;
485485
pTail = ((MI_LOAD_REGISTER_IMM *)pTail) + 1;
486486
}
487487

488488
// Add our BBS
489-
auto bbs = MI_BATCH_BUFFER_START::sInit();
489+
auto bbs = GfxFamily::cmdInitBatchBufferStart;
490490
bbs.setBatchBufferStartAddressGraphicsaddress472(static_cast<uint64_t>(batchBufferGpuAddress));
491491
bbs.setAddressSpaceIndicator(MI_BATCH_BUFFER_START::ADDRESS_SPACE_INDICATOR_PPGTT);
492492
*(MI_BATCH_BUFFER_START *)pTail = bbs;
@@ -497,7 +497,7 @@ void AUBCommandStreamReceiverHw<GfxFamily>::submitBatchBuffer(size_t engineIndex
497497

498498
// Add NOOPs as needed as our tail needs to be aligned
499499
while (engineInfo.tailRingBuffer % tailAlignment) {
500-
*(MI_NOOP *)pTail = MI_NOOP::sInit();
500+
*(MI_NOOP *)pTail = GfxFamily::cmdInitNoop;
501501
pTail = ((MI_NOOP *)pTail) + 1;
502502
engineInfo.tailRingBuffer = (uint32_t)ptrDiff(pTail, engineInfo.pRingBuffer);
503503
}
@@ -789,7 +789,7 @@ void AUBCommandStreamReceiverHw<GfxFamily>::addGUCStartMessage(uint64_t batchBuf
789789

790790
MI_BATCH_BUFFER_START *miBatchBufferStart = linearStream.getSpaceForCmd<MI_BATCH_BUFFER_START>();
791791
DEBUG_BREAK_IF(bufferSize != linearStream.getUsed());
792-
miBatchBufferStart->init();
792+
*miBatchBufferStart = GfxFamily::cmdInitBatchBufferStart;
793793
miBatchBufferStart->setBatchBufferStartAddressGraphicsaddress472(AUB::ptrToPPGTT(buffer.get()));
794794
miBatchBufferStart->setAddressSpaceIndicator(MI_BATCH_BUFFER_START::ADDRESS_SPACE_INDICATOR_PPGTT);
795795

‎runtime/command_stream/command_stream_receiver_hw.inl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -265,7 +265,7 @@ CompletionStamp CommandStreamReceiverHw<GfxFamily>::flushTask(
265265
if (stallingPipeControlOnNextFlushRequired) {
266266
stallingPipeControlOnNextFlushRequired = false;
267267
auto stallingPipeControlCmd = commandStream.getSpaceForCmd<PIPE_CONTROL>();
268-
*stallingPipeControlCmd = PIPE_CONTROL::sInit();
268+
*stallingPipeControlCmd = GfxFamily::cmdInitPipeControl;
269269
stallingPipeControlCmd->setCommandStreamerStallEnable(true);
270270
}
271271
initPageTableManagerRegisters(commandStreamCSR);

‎runtime/command_stream/experimental_command_buffer.inl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (C) 2018 Intel Corporation
2+
* Copyright (C) 2018-2019 Intel Corporation
33
*
44
* SPDX-License-Identifier: MIT
55
*
@@ -94,7 +94,7 @@ void ExperimentalCommandBuffer::addExperimentalCommands() {
9494
uint64_t gpuAddr = experimentalAllocation->getGpuAddress() + experimentalAllocationOffset;
9595

9696
auto semaphoreCmd = reinterpret_cast<MI_SEMAPHORE_WAIT *>(currentStream->getSpace(sizeof(MI_SEMAPHORE_WAIT)));
97-
*semaphoreCmd = MI_SEMAPHORE_WAIT::sInit();
97+
*semaphoreCmd = GfxFamily::cmdInitMiSemaphoreWait;
9898
semaphoreCmd->setCompareOperation(MI_SEMAPHORE_WAIT::COMPARE_OPERATION_SAD_EQUAL_SDD);
9999
semaphoreCmd->setSemaphoreDataDword(*semaphoreData);
100100
semaphoreCmd->setSemaphoreGraphicsAddress(gpuAddr);

‎runtime/command_stream/preemption.inl‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (C) 2017-2018 Intel Corporation
2+
* Copyright (C) 2017-2019 Intel Corporation
33
*
44
* SPDX-License-Identifier: MIT
55
*
@@ -36,7 +36,7 @@ void PreemptionHelper::applyPreemptionWaCmdsBegin(LinearStream *pCommandStream,
3636
preemptionMode == PreemptionMode::MidThread) {
3737
if (device.getWaTable()->waModifyVFEStateAfterGPGPUPreemption) {
3838
auto pCmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM)));
39-
*pCmd = MI_LOAD_REGISTER_IMM::sInit();
39+
*pCmd = GfxFamily::cmdInitLoadRegisterImm;
4040
pCmd->setRegisterOffset(CS_GPR_R0);
4141
pCmd->setDataDword(GPGPU_WALKER_COOKIE_VALUE_BEFORE_WALKER);
4242
}
@@ -51,7 +51,7 @@ void PreemptionHelper::applyPreemptionWaCmdsEnd(LinearStream *pCommandStream, co
5151
preemptionMode == PreemptionMode::MidThread) {
5252
if (device.getWaTable()->waModifyVFEStateAfterGPGPUPreemption) {
5353
auto pCmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM)));
54-
*pCmd = MI_LOAD_REGISTER_IMM::sInit();
54+
*pCmd = GfxFamily::cmdInitLoadRegisterImm;
5555
pCmd->setRegisterOffset(CS_GPR_R0);
5656
pCmd->setDataDword(GPGPU_WALKER_COOKIE_VALUE_AFTER_WALKER);
5757
}
@@ -66,7 +66,7 @@ void PreemptionHelper::programCsrBaseAddress(LinearStream &preambleCmdStream, De
6666
UNRECOVERABLE_IF(nullptr == preemptionCsr);
6767

6868
auto csr = reinterpret_cast<GPGPU_CSR_BASE_ADDRESS *>(preambleCmdStream.getSpace(sizeof(GPGPU_CSR_BASE_ADDRESS)));
69-
csr->init();
69+
*csr = GfxFamily::cmdInitGpgpuCsrBaseAddress;
7070
csr->setGpgpuCsrBaseAddress(preemptionCsr->getGpuAddressToPatch());
7171
}
7272
}
@@ -79,7 +79,7 @@ void PreemptionHelper::programStateSip(LinearStream &preambleCmdStream, Device &
7979

8080
if (isMidThreadPreemption || sourceLevelDebuggerActive) {
8181
auto sip = reinterpret_cast<STATE_SIP *>(preambleCmdStream.getSpace(sizeof(STATE_SIP)));
82-
sip->init();
82+
*sip = GfxFamily::cmdInitStateSip;
8383
auto sipType = SipKernel::getSipKernelType(device.getHardwareInfo().pPlatform->eRenderCoreFamily, sourceLevelDebuggerActive);
8484
sip->setSystemInstructionPointer(device.getExecutionEnvironment()->getBuiltIns()->getSipKernel(sipType, device).getSipAllocation()->getGpuAddressToPatch());
8585
}

‎runtime/command_stream/tbx_command_stream_receiver_hw.inl‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -275,22 +275,22 @@ void TbxCommandStreamReceiverHw<GfxFamily>::submitBatchBuffer(size_t engineIndex
275275
pTail = engineInfo.pRingBuffer;
276276
} else if (engineInfo.tailRingBuffer == 0) {
277277
// Add a LRI if this is our first submission
278-
auto lri = MI_LOAD_REGISTER_IMM::sInit();
278+
auto lri = GfxFamily::cmdInitLoadRegisterImm;
279279
lri.setRegisterOffset(AubMemDump::computeRegisterOffset(csTraits.mmioBase, 0x2244));
280280
lri.setDataDword(0x00010000);
281281
*(MI_LOAD_REGISTER_IMM *)pTail = lri;
282282
pTail = ((MI_LOAD_REGISTER_IMM *)pTail) + 1;
283283
}
284284

285285
// Add our BBS
286-
auto bbs = MI_BATCH_BUFFER_START::sInit();
286+
auto bbs = GfxFamily::cmdInitBatchBufferStart;
287287
bbs.setBatchBufferStartAddressGraphicsaddress472(AUB::ptrToPPGTT(batchBuffer));
288288
bbs.setAddressSpaceIndicator(MI_BATCH_BUFFER_START::ADDRESS_SPACE_INDICATOR_PPGTT);
289289
*(MI_BATCH_BUFFER_START *)pTail = bbs;
290290
pTail = ((MI_BATCH_BUFFER_START *)pTail) + 1;
291291

292292
// Add a NOOP as our tail needs to be aligned to a QWORD
293-
*(MI_NOOP *)pTail = MI_NOOP::sInit();
293+
*(MI_NOOP *)pTail = GfxFamily::cmdInitNoop;
294294
pTail = ((MI_NOOP *)pTail) + 1;
295295

296296
// Compute our new ring tail.

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