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airliedairlied
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Merge tag 'amd-drm-fixes-6.11-2024-08-08' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.11-2024-08-08: amdgpu: - DMCUB fix - Fix DET programming on some DCNs - DCC fixes - DCN 4.0.1 fixes - SMU 14.0.x update - MMHUB fix - DCN 3.1.4 fix - GC 12.0 fixes - Fix soft recovery error propogation - SDMA 7.0 fixes - DSC fix drm buddy: - Add start address to trim function Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240808161134.1227671-1-alexander.deucher@amd.com
2 parents 062fd0a + 6ad9daf commit a507e75

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18 files changed

+178
-20
lines changed

18 files changed

+178
-20
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,8 @@ struct amdgpu_gmc_funcs {
156156
uint64_t addr, uint64_t *flags);
157157
/* get the amount of memory used by the vbios for pre-OS console */
158158
unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev);
159+
/* get the DCC buffer alignment */
160+
unsigned int (*get_dcc_alignment)(struct amdgpu_device *adev);
159161

160162
enum amdgpu_memory_partition (*query_mem_partition_mode)(
161163
struct amdgpu_device *adev);
@@ -363,6 +365,10 @@ struct amdgpu_gmc {
363365
(adev)->gmc.gmc_funcs->override_vm_pte_flags \
364366
((adev), (vm), (addr), (pte_flags))
365367
#define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))
368+
#define amdgpu_gmc_get_dcc_alignment(adev) ({ \
369+
typeof(adev) _adev = (adev); \
370+
_adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \
371+
})
366372

367373
/**
368374
* amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR

‎drivers/gpu/drm/amd/amdgpu/amdgpu_job.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -264,9 +264,8 @@ amdgpu_job_prepare_job(struct drm_sched_job *sched_job,
264264
struct dma_fence *fence = NULL;
265265
int r;
266266

267-
/* Ignore soft recovered fences here */
268267
r = drm_sched_entity_error(s_entity);
269-
if (r && r != -ENODATA)
268+
if (r)
270269
goto error;
271270

272271
if (!fence && job->gang_submit)

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c‎

Lines changed: 34 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -456,6 +456,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,
456456
u64 vis_usage = 0, max_bytes, min_block_size;
457457
struct amdgpu_vram_mgr_resource *vres;
458458
u64 size, remaining_size, lpfn, fpfn;
459+
unsigned int adjust_dcc_size = 0;
459460
struct drm_buddy *mm = &mgr->mm;
460461
struct drm_buddy_block *block;
461462
unsigned long pages_per_block;
@@ -511,7 +512,19 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,
511512
/* Allocate blocks in desired range */
512513
vres->flags |= DRM_BUDDY_RANGE_ALLOCATION;
513514

515+
if (bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC &&
516+
adev->gmc.gmc_funcs->get_dcc_alignment)
517+
adjust_dcc_size = amdgpu_gmc_get_dcc_alignment(adev);
518+
514519
remaining_size = (u64)vres->base.size;
520+
if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size) {
521+
unsigned int dcc_size;
522+
523+
dcc_size = roundup_pow_of_two(vres->base.size + adjust_dcc_size);
524+
remaining_size = (u64)dcc_size;
525+
526+
vres->flags |= DRM_BUDDY_TRIM_DISABLE;
527+
}
515528

516529
mutex_lock(&mgr->lock);
517530
while (remaining_size) {
@@ -521,8 +534,11 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,
521534
min_block_size = mgr->default_page_size;
522535

523536
size = remaining_size;
524-
if ((size >= (u64)pages_per_block << PAGE_SHIFT) &&
525-
!(size & (((u64)pages_per_block << PAGE_SHIFT) - 1)))
537+
538+
if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size)
539+
min_block_size = size;
540+
else if ((size >= (u64)pages_per_block << PAGE_SHIFT) &&
541+
!(size & (((u64)pages_per_block << PAGE_SHIFT) - 1)))
526542
min_block_size = (u64)pages_per_block << PAGE_SHIFT;
527543

528544
BUG_ON(min_block_size < mm->chunk_size);
@@ -553,6 +569,22 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,
553569
}
554570
mutex_unlock(&mgr->lock);
555571

572+
if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size) {
573+
struct drm_buddy_block *dcc_block;
574+
unsigned long dcc_start;
575+
u64 trim_start;
576+
577+
dcc_block = amdgpu_vram_mgr_first_block(&vres->blocks);
578+
/* Adjust the start address for DCC buffers only */
579+
dcc_start =
580+
roundup((unsigned long)amdgpu_vram_mgr_block_start(dcc_block),
581+
adjust_dcc_size);
582+
trim_start = (u64)dcc_start;
583+
drm_buddy_block_trim(mm, &trim_start,
584+
(u64)vres->base.size,
585+
&vres->blocks);
586+
}
587+
556588
vres->base.start = 0;
557589
size = max_t(u64, amdgpu_vram_mgr_blocks_size(&vres->blocks),
558590
vres->base.size);

‎drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -202,6 +202,12 @@ static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {
202202
SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
203203
};
204204

205+
static const struct soc15_reg_golden golden_settings_gc_12_0[] = {
206+
SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f),
207+
SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000),
208+
SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020)
209+
};
210+
205211
#define DEFAULT_SH_MEM_CONFIG \
206212
((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
207213
(SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -3432,6 +3438,24 @@ static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev)
34323438
WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
34333439
}
34343440

3441+
static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev)
3442+
{
3443+
if (amdgpu_sriov_vf(adev))
3444+
return;
3445+
3446+
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3447+
case IP_VERSION(12, 0, 0):
3448+
case IP_VERSION(12, 0, 1):
3449+
if (adev->rev_id == 0)
3450+
soc15_program_register_sequence(adev,
3451+
golden_settings_gc_12_0,
3452+
(const u32)ARRAY_SIZE(golden_settings_gc_12_0));
3453+
break;
3454+
default:
3455+
break;
3456+
}
3457+
}
3458+
34353459
static int gfx_v12_0_hw_init(void *handle)
34363460
{
34373461
int r;
@@ -3472,6 +3496,9 @@ static int gfx_v12_0_hw_init(void *handle)
34723496
}
34733497
}
34743498

3499+
if (!amdgpu_emu_mode)
3500+
gfx_v12_0_init_golden_registers(adev);
3501+
34753502
adev->gfx.is_poweron = true;
34763503

34773504
if (get_gb_addr_config(adev))

‎drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -542,6 +542,23 @@ static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev)
542542
return 0;
543543
}
544544

545+
static unsigned int gmc_v12_0_get_dcc_alignment(struct amdgpu_device *adev)
546+
{
547+
unsigned int max_tex_channel_caches, alignment;
548+
549+
if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) &&
550+
amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1))
551+
return 0;
552+
553+
max_tex_channel_caches = adev->gfx.config.max_texture_channel_caches;
554+
if (is_power_of_2(max_tex_channel_caches))
555+
alignment = (unsigned int)(max_tex_channel_caches / SZ_4);
556+
else
557+
alignment = roundup_pow_of_two(max_tex_channel_caches);
558+
559+
return (unsigned int)(alignment * max_tex_channel_caches * SZ_1K);
560+
}
561+
545562
static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = {
546563
.flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb,
547564
.flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid,
@@ -551,6 +568,7 @@ static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = {
551568
.get_vm_pde = gmc_v12_0_get_vm_pde,
552569
.get_vm_pte = gmc_v12_0_get_vm_pte,
553570
.get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size,
571+
.get_dcc_alignment = gmc_v12_0_get_dcc_alignment,
554572
};
555573

556574
static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,8 @@ static uint32_t mmhub_v4_1_0_get_invalidate_req(unsigned int vmid,
8080
/* invalidate using legacy mode on vmid*/
8181
req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
8282
PER_VMID_INVALIDATE_REQ, 1 << vmid);
83-
req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
83+
/* Only use legacy inv on mmhub side */
84+
req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
8485
req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
8586
req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
8687
req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

‎drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1575,8 +1575,7 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
15751575
ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
15761576
SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
15771577
SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0) |
1578-
SDMA_PKT_COPY_LINEAR_HEADER_CPV((copy_flags &
1579-
(AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)) ? 1 : 0);
1578+
SDMA_PKT_COPY_LINEAR_HEADER_CPV(1);
15801579

15811580
ib->ptr[ib->length_dw++] = byte_count - 1;
15821581
ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
@@ -1590,6 +1589,8 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
15901589
((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) |
15911590
((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) |
15921591
SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1);
1592+
else
1593+
ib->ptr[ib->length_dw++] = 0;
15931594
}
15941595

15951596
/**
@@ -1616,7 +1617,7 @@ static void sdma_v7_0_emit_fill_buffer(struct amdgpu_ib *ib,
16161617

16171618
static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = {
16181619
.copy_max_bytes = 0x400000,
1619-
.copy_num_dw = 7,
1620+
.copy_num_dw = 8,
16201621
.emit_copy_buffer = sdma_v7_0_emit_copy_buffer,
16211622
.fill_max_bytes = 0x400000,
16221623
.fill_num_dw = 5,

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1270,6 +1270,9 @@ static bool is_dsc_need_re_compute(
12701270
}
12711271
}
12721272

1273+
if (new_stream_on_link_num == 0)
1274+
return false;
1275+
12731276
/* check current_state if there stream on link but it is not in
12741277
* new request state
12751278
*/

‎drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -185,8 +185,7 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub,
185185
else
186186
copy_settings_data->flags.bitfields.force_wakeup_by_tps3 = 0;
187187

188-
189-
dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
188+
dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
190189

191190
return true;
192191
}

‎drivers/gpu/drm/amd/display/dc/dml/Makefile‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,8 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcfla
8383
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_rcflags)
8484
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_rcflags)
8585
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_rcflags)
86+
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn314/display_mode_vba_314.o := $(dml_rcflags)
87+
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn314/display_rq_dlg_calc_314.o := $(dml_rcflags)
8688
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_rcflags)
8789
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags)
8890
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_rcflags)

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