From 2591b2dfaa2c1243bbdd99d7d28f9eddbd7aeb44 Mon Sep 17 00:00:00 2001 From: Aadarsh Date: Mon, 2 Sep 2024 10:37:58 +0530 Subject: [PATCH 1/2] Update README.md --- docs/Verilog/Intro/README.md | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/Verilog/Intro/README.md b/docs/Verilog/Intro/README.md index fa478fc..0fd9f7c 100644 --- a/docs/Verilog/Intro/README.md +++ b/docs/Verilog/Intro/README.md @@ -73,7 +73,10 @@ registers. In this approach, the 'assign' statement is used. An assign statement is a continuous statement where any signal changes on the right-hand side will update the output signal. Changes in the inputs are continuously monitored. Any synthesizable code is called RTL code. -Gate-Level: This is the lowest level of abstraction. Here, the circuit is + +### Gate-Level: + +This is the lowest level of abstraction. Here, the circuit is described by logical links and their timing properties. The module is implemented in terms of logic gates and interconnections between these gates. It resembles a schematic drawing with components connected with From 71517a1a1e70167eb4698d2501d900f53c4455c1 Mon Sep 17 00:00:00 2001 From: Aadarsh Date: Mon, 2 Sep 2024 10:44:46 +0530 Subject: [PATCH 2/2] Update README.md --- docs/Verilog/Intro/README.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/Verilog/Intro/README.md b/docs/Verilog/Intro/README.md index 0fd9f7c..2029544 100644 --- a/docs/Verilog/Intro/README.md +++ b/docs/Verilog/Intro/README.md @@ -110,7 +110,8 @@ lower levels of abstraction. - Can be optimized for timing, power, and area, allowing for more efficient designs. - Can be used for both simulation and synthesis. -Cons + +#### Cons - More difficult to write and understand than the behavioral level. - Can be less portable than the behavioral level, since the same code may not synthesize correctly across different architectures. @@ -124,7 +125,8 @@ design is more complex. - Provides the most detailed view of the hardware implementation. - Highly optimized for area, power, and performance. - Ideal for final verification of the design. -Cons + +#### Cons - Very difficult to write and understand. - Not portable: The code is specific to a particular hardware architecture. - Verification can be very time-consuming and difficult, especially for