Merge pull request #193 from kvark/stm32l1

Added basic hal implementation for STM32L1

Author: farcaller

.travis.yml

@@ -18,4 +18,5 @@ env:
   matrix:
     - PLATFORM=lpc17xx
     - PLATFORM=stm32f4
+    - PLATFORM=stm32l1
     - PLATFORM=k20

Rakefile

@@ -179,6 +179,8 @@ when 'k20'
   task :build_all => [:build_blink_k20, :build_blink_k20_isr]
 when 'stm32f4'
   task :build_all => [:build_blink_stm32f4]
+when 'stm32l1'
+  task :build_all => [:build_blink_stm32l1]
 else
   task :build_all => [:build_empty, :build_blink]
 end

apps/app_blink_stm32l1.rs

@@ -0,0 +1,31 @@
+#![feature(phase)]
+#![crate_type="staticlib"]
+#![no_std]
+
+extern crate core;
+extern crate zinc;
+
+#[no_mangle]
+pub unsafe fn main() {
+  use core::default::Default;
+  use zinc::hal::pin::GPIO;
+  use zinc::hal::stm32l1::{init, pin, timer};
+  use zinc::hal::timer::Timer;
+  zinc::hal::mem_init::init_stack();
+  zinc::hal::mem_init::init_data();
+
+  let sys_clock: init::SystemClockSource = Default::default();
+
+  let led1 = pin::Pin::new(pin::PortA, 5,
+    pin::GpioOut(pin::OutPushPull, pin::VeryLow),
+    pin::PullNone);
+
+  let timer = timer::Timer::new(timer::Timer2, sys_clock.to_speed_khz(), 0);
+
+  loop {
+    led1.set_high();
+    timer.wait_ms(1);
+    led1.set_low();
+    timer.wait_ms(1);
+  }
+}

platforms.yml

@@ -4,5 +4,7 @@ lpc17xx:
     - mcu_has_spi
 stm32f4:
   arch:   cortex_m4
+stm32l1:
+  arch:   cortex_m3
 k20:
   arch:   cortex_m4

src/zinc/hal/mod.rs

@@ -24,6 +24,7 @@ and each such struct has a `setup()` method that configures the hardware
 
 pub mod lpc17xx;
 pub mod stm32f4;
+pub mod stm32l1;
 pub mod k20;
 
 mod cortex_common;

src/zinc/hal/stm32f4/init.rs

@@ -13,7 +13,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-//! Routines for initialization of NXP LPC17xx.
+//! Routines for initialization of STM32F4.
 //!
 //! This module includes code for setting up the clock, flash, access time and
 //! performing initial peripheral configuration.

src/zinc/hal/stm32f4/mod.rs

@@ -15,8 +15,8 @@
 
 //! HAL for STM32F4.
 
-pub mod pin;
 pub mod init;
 pub mod gpio;
 pub mod peripheral_clock;
+pub mod pin;
 pub mod timer;

src/zinc/hal/stm32l1/init.rs

@@ -0,0 +1,181 @@
+// Zinc, the bare metal stack for rust.
+// Copyright 2014 Dzmitry "kvark" Malyshau <kvarkus@gmail.com>
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//! Routines for initialization of STM32L1.
+//!
+//! This module includes code for setting up the clock, flash, access time and
+//! performing initial peripheral configuration.
+
+//use hal::mem_init::init_data;
+use core::default::Default;
+use core::intrinsics::abort;
+
+#[path="../../util/ioreg.rs"] mod ioreg;
+#[path="../../util/wait_for.rs"] mod wait_for;
+
+/// Phase-locked loop configuration.
+pub struct PllConfig;
+
+/// Multi-speed internal clock divisor.
+pub enum MsiSpeed {
+  /// 65_536 kHz
+  Msi65   = 0,
+  /// 131_072 kHz
+  Msi131  = 1,
+  /// 262_144 kHz
+  Msi262  = 2,
+  /// 524_288 kHz
+  Msi524  = 3,
+  /// 1048 MHz
+  Msi1048 = 4,
+  /// 2097 MHz
+  Msi2097 = 5,
+  /// 4194 MHz
+  Msi4194 = 6,
+}
+
+/// System clock source.
+pub enum SystemClockSource {
+  /// High-speed internal oscillator, 16MHz.
+  SystemClockHSI,
+  /// High-speed external oscillator with configurable frequency.
+  SystemClockHSE(u32),
+  /// PLL.
+  SystemClockPLL(PllConfig),
+  /// Multi-speed internal clock,
+  SystemClockMSI(MsiSpeed),
+}
+
+impl Default for SystemClockSource {
+  fn default() -> SystemClockSource {
+    SystemClockMSI(Msi2097)
+  }
+}
+
+impl SystemClockSource {
+  /// Get the system clock speed in kHz
+  pub fn to_speed_khz(&self) -> u32 {
+    match *self {
+        SystemClockHSI => 16<<10,
+        SystemClockMSI(Msi2097) => 2097,
+        _ => unsafe { abort() }, //TODO(kvark)
+    }
+  }
+}
+
+// TODO(farcaller): this mod is pub as it's being used in peripheral_clock.rs.
+//                  This is not the best design solution and a good reason to
+//                  split RCC into distinct registers.
+#[allow(missing_doc)]
+pub mod reg {
+  use util::volatile_cell::VolatileCell;
+  use core::ops::Drop;
+
+  ioregs!(RCC = {
+    0x00 => reg32 cr {          // clock control
+      31..0 => clock_control : rw,
+    },
+    0x04 => reg32 icscr {       // internal clock sources calibration
+      31..0 => clock_calibration : rw,
+    },
+    0x08 => reg32 cfgr {        // clock configuration
+      31..0 => clock_config : rw,
+    },
+    0x0C => reg32 cir {         // clock interrupt
+      31..0 => clock_interrupt : rw,
+    },
+    0x10 => reg32 ahbrstr {     // AHB peripheral reset
+      31..0 => reset : rw,
+    },
+    0x14 => reg32 apb2rstr {    // APB2 peripheral reset
+      31..0 => reset : rw,
+    },
+    0x18 => reg32 apb1rstr {    // APB1 peripheral reset
+      31..0 => reset : rw,
+    },
+    0x1C => reg32 ahbenr {      // AHB peripheral clock enable
+      31..0 => enable : rw,
+    },
+    0x20 => reg32 apb2enr {     // APB2 peripheral clock enable
+      31..0 => enable : rw,
+    },
+    0x24 => reg32 apb1enr {     // ABB1 peripheral clock enable
+      31..0 => enable : rw,
+    },
+    0x28 => reg32 ahblpenr {    // AHB peripheral clock enable in low power mode
+      31..0 => enable_low_power : rw,
+    },
+    0x2C => reg32 apb2lpenr {   // APB2 peripheral clock enable in low power mode
+      31..0 => enable_low_power : rw,
+    },
+    0x30 => reg32 apb1lpenr {   // APB1 peripheral clock enable in low power mode
+      31..0 => enable_low_power : rw,
+    },
+    0x34 => reg32 csr {         // control/status
+      31..0 => status : rw,
+    },
+  })
+
+  ioregs!(FLASH = {
+    0x00 => reg32 acr {     // access control
+      31..0 => access_control : rw,
+    },
+    0x04 => reg32 pecr {    // program/erase control
+      31..0 => program_control : rw,
+    },
+    0x08 => reg32 pdkeyr {  // power down key
+      31..0 => power_down : rw,
+    },
+    0x0C => reg32 pekeyr {  // program/erase key
+      31..0 => program_key : rw,
+    },
+    0x10 => reg32 prtkeyr { // program memory key
+      31..0 => program_memory : rw,
+    },
+    0x14 => reg32 optkeyr { // option byte key
+      31..0 => option_byte : rw,
+    },
+    0x18 => reg32 sr {      // status register
+      31..0 => status : rw,
+    },
+    0x1C => reg32 obr {     // option byte
+      31..0 => option : rw,
+    },
+    0x20 => reg32 wrpr {    // write protection
+      31..0 => protect : rw,
+    },
+    0x28 => reg32 wrpr1 {   // write protection register 1
+      31..0 => protect : rw,
+    },
+    0x2C => reg32 wrpr2 {   // write protection register 2
+      31..0 => protect : rw,
+    },
+  })
+
+  ioregs!(PWR = {
+    0x0 => reg32 cr {   // power control
+      31..0 => control : rw,
+    },
+    0x4 => reg32 csr {  // power control/status
+      31..0 => status : rw,
+    },
+  })
+
+  extern {
+    #[link_name="stm32l1_iomem_RCC"] pub static RCC: RCC;
+    #[link_name="stm32l1_iomem_FLASH"] pub static FLASH: FLASH;
+    #[link_name="stm32l1_iomem_PWR"] pub static PWR: PWR;
+  }
+}

src/zinc/hal/stm32l1/iomem.ld

@@ -0,0 +1,17 @@
+INCLUDE ./src/zinc/hal/cortex_m3/armmem.ld
+
+stm32l1_iomem_TIM2  = 0x40000000;
+
+stm32l1_iomem_PWR   = 0x40007000;
+
+stm32l1_iomem_FLASH = 0x40023C00;
+stm32l1_iomem_RCC   = 0x40023800;
+
+stm32l1_iomem_GPIOA = 0x40020000;
+stm32l1_iomem_GPIOB = 0x40020400;
+stm32l1_iomem_GPIOC = 0x40020800;
+stm32l1_iomem_GPIOD = 0x40020c00;
+stm32l1_iomem_GPIOE = 0x40021000;
+stm32l1_iomem_GPIOF = 0x40021800;
+stm32l1_iomem_GPIOG = 0x40021C00;
+stm32l1_iomem_GPIOH = 0x40021400;

src/zinc/hal/stm32l1/layout.ld

@@ -0,0 +1,17 @@
+__STACK_BASE = 0x20008000;  /* end of ram */
+_boot_checksum = 0; /* TODO(farcaller): extract this to lpc code only */
+_data_load = LOADADDR(.data);
+
+INCLUDE ./src/zinc/hal/stm32l1/iomem.ld
+
+ENTRY(main)
+
+MEMORY
+{
+    rom(RX)     : ORIGIN = 0x08000000, LENGTH = 6 * 64K
+    ram(WAIL)   : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+REGION_ALIAS("vectors", rom);
+
+INCLUDE ./src/zinc/hal/layout_common.ld