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Commit 00dd128

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DM: update SAMD51 ADC sampling rate
1 parent a959a48 commit 00dd128

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+5
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cores/arduino/wiring.c

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -109,14 +109,16 @@ void init( void )
109109
// Initialize Analog Controller
110110
// Setting clock
111111
#if defined(__SAMD51__)
112-
GCLK->PCHCTRL[ADC0_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); //use clock generator 1 (48Mhz)
112+
//Set ADC sampling rate to 1/ ( 1/(120MHz/16) ) * (30 + 1) = 241935 Samples/Sec
113+
114+
GCLK->PCHCTRL[ADC0_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); //use clock generator 1 (48Mhz)
113115

114-
ADC0->CTRLA.bit.PRESCALER = ADC_CTRLA_PRESCALER_DIV256_Val;
116+
ADC0->CTRLA.bit.PRESCALER = ADC_CTRLA_PRESCALER_DIV16_Val;
115117
ADC0->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_10BIT_Val;
116118

117119
while( ADC0->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB ); //wait for sync
118120

119-
ADC0->SAMPCTRL.reg = 0x3f; // Set max Sampling Time Length
121+
ADC0->SAMPCTRL.reg = 30; // ampling Time Length
120122

121123
while( ADC0->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL ); //wait for sync
122124

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