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Copy file name to clipboardExpand all lines: content/Video_Display.md
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@@ -7,12 +7,12 @@ A *dot* is the shortest period over which the PPU can output one pixel: is it eq
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### FF41 - STAT (LCD Status) (R/W)
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```
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Bit 6 - LYC=LY Interrupt (1=Enable) (Read/Write)
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Bit 5 - Mode 2 OAM Interrupt (1=Enable) (Read/Write)
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Bit 4 - Mode 1 VBlank Interrupt (1=Enable) (Read/Write)
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Bit 3 - Mode 0 HBlank Interrupt (1=Enable) (Read/Write)
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Bit 2 - LYC=LY Flag (0=Different, 1=Equal) (Read Only)
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Bit 1-0 - Mode Flag (Mode 0-3, see below) (Read Only)
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Bit 6 - LYC=LY STAT Interrupt source (1=Enable) (Read/Write)
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Bit 5 - Mode 2 OAM STAT Interrupt source (1=Enable) (Read/Write)
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Bit 4 - Mode 1 VBlank STAT Interrupt source (1=Enable) (Read/Write)
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Bit 3 - Mode 0 HBlank STAT Interrupt source (1=Enable) (Read/Write)
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Bit 2 - LYC=LY Flag (0=Different, 1=Equal) (Read Only)
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Bit 1-0 - Mode Flag (Mode 0-3, see below) (Read Only)
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0: In HBlank
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1: In VBlank
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2: Searching OAM
@@ -92,24 +92,36 @@ milliseconds.
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### INT 48 - STAT Interrupt
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There are various reasons for this interrupt to occur as described by
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the STAT register (\$FF41). One very popular reason is to indicate to
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the user when the video hardware is about to redraw a given LCD line.
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This can be useful for dynamically controlling the SCX/SCY registers
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($FF43/$FF42) to perform special video effects.
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There are various sources which can trigger this interrupt to occur as
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described by the [STAT register (\$FF41)](#ff41-stat-lcd-status-r-w).
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One very popular use is to indicate to the user when the video
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hardware is about to redraw a given LCD line. This can be useful for
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dynamically controlling the SCX/SCY registers ($FF43/$FF42) to [perform
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special video effects](https://github.com/BlitterObjectBob/DeadCScroll).
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Example application: set LYC to WY, enable LY=LYC interrupt, and have
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the handler disable sprites. This can be used if you use the window for
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a text box (at the bottom of the screen), and you want sprites to be
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hidden by the text box.
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The various STAT interrupt sources (modes 0-2 and LYC=LY) have their
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state (inactive/low and active/high) logically ORed into a shared
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STAT interrupt line if their respective enable bit is turned on.
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A STAT interrupt will be triggered by a rising edge (transition from
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low-to-high) on the STAT interrupt line.
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::: warning
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As mentioned in the description of the STAT register, the PPU cycles
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through the different modes in a fixed order. If we set the STAT bits
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in a way that they would interrupt the CPU at two
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consecutive modes, then the second interrupt will not trigger. So for example,
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if we enable the interrupts for Mode 0 and Mode 1,
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the Mode 1 interrupt will not trigger.
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If a STAT interrupt source logically ORs the interrupt line high while
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(or immediately after) it's already set high by another source, then
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there will be no low-to-high transition and so no interrupt will occur.
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This phenomenon is known as "STAT blocking" ([test ROM example](https://github.com/Gekkio/mooneye-gb/blob/2d52008228557f9e713545e702d5b7aa233d09bb/tests/acceptance/ppu/stat_irq_blocking.s#L21-L22)).
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As mentioned in the description of the [STAT register](#ff41-stat-lcd-status-r-w),
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the PPU cycles through the different modes in a fixed order. So for
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example, if interrupts are enabled for two consecutive modes such as
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Mode 0 and Mode 1, then no interrupt will trigger for Mode 1 (since
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the STAT interrupt line won't have a chance to go low between them).
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