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Copy file name to clipboardExpand all lines: src/Audio.md
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@@ -54,7 +54,7 @@ The SGB2 rectifies this issue.
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All interfaces to the APU use **durations** instead of frequencies, which may be confusing as signal theory and music are more typically based on the latter.
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Thus, durations will be expressed from their frequencies: for example, a "256 Hz tick" means "1 ∕ 256th of a second".
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The length of APU ticks is not affected by [CGB double speed](<#FF4D — KEY1 (CGB Mode only): Prepare speed switch>), so the APU works just the same regardless of CPU speed.
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The length of APU ticks is not affected by [CGB double speed](<#FF4D — KEY1/SPD (CGB Mode only): Prepare speed switch>), so the APU works just the same regardless of CPU speed.
Copy file name to clipboardExpand all lines: src/Audio_Registers.md
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@@ -12,7 +12,7 @@ As a rule of thumb, for any `x` in `1`, `2`, `3`, `4`:
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...but there are some exceptions.
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One of the pitfalls of the `NRxy` naming convention is that the register's purpose is not immediately clear from its name, so some alternative names have been proposed, [such as `AUDENA` for `NR52`](https://github.com/gbdev/hardware.inc/blob/05f5a9b6c7172abe1d7488080c1c050284c09226/hardware.inc#L415).
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One of the pitfalls of the `NRxy` naming convention is that the register's purpose is not immediately clear from its name, so some alternative `AUD*`names have been proposed, [such as `AUDENA` for `NR52`](https://github.com/gbdev/hardware.inc/blob/8d4432e5796bffe2e13c438013285c5f11c37b99/hardware.inc#L910).
Copy file name to clipboardExpand all lines: src/Audio_details.md
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@@ -84,7 +84,7 @@ Same, but with channels 3 and 4.
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### DIV-APU
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A "DIV-APU" counter is increased every time `DIV`'s bit 4 (5 in [double-speed mode](<#FF4D — KEY1 (CGB Mode only): Prepare speed switch>)) goes from 1 to 0, therefore at a frequency of 512 Hz (regardless of whether double-speed is active).
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A "DIV-APU" counter is increased every time `DIV`'s bit 4 (5 in [double-speed mode](<#FF4D — KEY1/SPD (CGB Mode only): Prepare speed switch>)) goes from 1 to 0, therefore at a frequency of 512 Hz (regardless of whether double-speed is active).
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Thus, the counter can be made to increase faster by writing to `DIV` while its relevant bit is set (which clears `DIV`, and triggers the falling edge).
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The following events occur every <var>N</var> DIV-APU ticks:
Copy file name to clipboardExpand all lines: src/CGB_Registers.md
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### LCD VRAM DMA Transfers
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One of the pitfalls of the `HDMAx` naming convention is that the register's purpose is not immediately clear from its name, so some alternative `VDMA_*` names have been proposed, [such as `VDMA_LEN` for `HDMA5`](https://github.com/gbdev/hardware.inc/blob/8d4432e5796bffe2e13c438013285c5f11c37b99/hardware.inc#L919).
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880us LED ON signal. Even though being generally CGB compatible, the GBA
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does not include an infra-red port.
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### FF4C — KEY0 (CGB Mode only): CPU mode select
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### FF4C — KEY0/SYS (CGB Mode only): CPU mode select
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This GBC-only register (which is not officially documented) is written only by the CGB boot ROM,
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as it gets locked after the bootrom finish execution (by a write to the [BANK register](<#Monochrome models (DMG0, DMG, MGB)>)).
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the DMG prioritizes objects by x-coordinate, the CGB prioritizes them by
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location in OAM. This flag is set by the CGB bios after checking the game's CGB compatibility.
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OPRI has an effect if a [PGB](<#PGB mode>) value (`0xX8`, `0xXC`) is written to [KEY0](<#FF4C — KEY0 (CGB Mode only): CPU mode select>) but STOP hasn't been executed yet, and the write takes effect instantly.
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OPRI has an effect if a [PGB](<#PGB mode>) value (`0xX8`, `0xXC`) is written to [KEY0](<#FF4C — KEY0/SYS (CGB Mode only): CPU mode select>) but STOP hasn't been executed yet, and the write takes effect instantly.
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:::warning TO BE VERIFIED
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@@ -266,7 +268,7 @@ It is not known if triggering a PSM NMI, which remaps the boot ROM, has an effec
Copy file name to clipboardExpand all lines: src/Power_Up_Sequence.md
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@@ -86,8 +86,8 @@ Then, like the monochrome boot ROMs, the header logo is checked *from the buffer
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For unknown reasons, however, only the first half of the logo is checked, despite the full logo being present in the HRAM buffer.
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Finally, the boot ROM fades all BG palettes to white, and sets the hardware to compatibility mode.
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If [the CGB compatibility byte](<#0143 — CGB flag>) indicates CGB compatibility, the byte is written directly to [`KEY0`](<#FF4C — KEY0 (CGB Mode only): CPU mode select>), potentially [enabling "PGB mode"](<#PGB mode>);
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otherwise, $04 is written to [`KEY0`](<#FF4C — KEY0 (CGB Mode only): CPU mode select>) (enabling DMG compatibility mode in the CPU),
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If [the CGB compatibility byte](<#0143 — CGB flag>) indicates CGB compatibility, the byte is written directly to [`KEY0`](<#FF4C — KEY0/SYS (CGB Mode only): CPU mode select>), potentially [enabling "PGB mode"](<#PGB mode>);
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otherwise, $04 is written to [`KEY0`](<#FF4C — KEY0/SYS (CGB Mode only): CPU mode select>) (enabling DMG compatibility mode in the CPU),
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$01 is written to [`OPRI`](<#FF6C — OPRI (CGB Mode only): Object priority mode>) (enabling [DMG OBJ priority](<#Object Priority and Conflicts>)), and the [compatibility palettes](<#Compatibility palettes>) are written.
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Additionally, the DMG logo tilemap is written [if the compatibility requests it](<#Compatibility palettes>).
Copy file name to clipboardExpand all lines: src/Rendering.md
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The most famous raster effect is modifying the [scrolling registers](<#LCD Position and Scrolling>) between scanlines to create a ["wavy" effect](https://gbdev.io/guides/deadcscroll#effects).
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A "**dot**" = one 2<sup>22</sup> Hz (≅ 4.194 MHz) time unit.
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Dots remain the same regardless of whether the CPU is in [Double Speed mode](<#FF4D — KEY1 (CGB Mode only): Prepare speed switch>), so there are 4 dots per Single Speed M-cycle, and 2 per Double Speed M-cycle.
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Dots remain the same regardless of whether the CPU is in [Double Speed mode](<#FF4D — KEY1/SPD (CGB Mode only): Prepare speed switch>), so there are 4 dots per Single Speed M-cycle, and 2 per Double Speed M-cycle.
Copy file name to clipboardExpand all lines: src/The_Cartridge_Header.md
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`$80` | The game supports CGB enhancements, but is backwards compatible with monochrome Game Boys
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`$C0` | The game works on CGB only (the hardware ignores bit 6, so this really functions the same as `$80`)
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Setting bit 7 will trigger a write of this register value to [KEY0 register](<#FF4C — KEY0 (CGB Mode only): CPU mode select>) which sets the CPU mode.
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Setting bit 7 will trigger a write of this register value to [KEY0 register](<#FF4C — KEY0/SYS (CGB Mode only): CPU mode select>) which sets the CPU mode.
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