drivers: riscv: imsic: add SMP initialization support

Add automatic IMSIC initialization for secondary CPUs in SMP systems,
following the same pattern as the CLINT timer initialization.

Changes:
- Fixed IMSIC IRQ registration to avoid duplicate handler registration:
  * Only hart 0 (instance 0) registers the global MEXT IRQ handler via
    IRQ_CONNECT()
  * Secondary hart instances only enable MEXT locally without
    registering duplicate handlers

- Added z_riscv_imsic_secondary_init() function:
  * Called automatically from arch_secondary_cpu_init() on each secondary CPU
  * Configures EIDELIVERY to enable interrupt delivery in MMSI mode
  * Sets EITHRESHOLD to 0 to allow all interrupt priorities
  * Enables MEXT interrupt on the current CPU
  * Follows the CLINT smp_timer_init() pattern for per-CPU initialization

- Integrated with arch/riscv/core/smp.c:
  * arch_secondary_cpu_init() now calls z_riscv_imsic_secondary_init()
    when CONFIG_RISCV_IMSIC && CONFIG_SMP are enabled
  * Ensures IMSIC is properly initialized before secondary CPUs become
    active

This allows IMSIC to work correctly in SMP configurations without
requiring manual initialization in application code. Each CPU's IMSIC
file is configured automatically during SMP boot.

Note: IMSIC CSRs are accessed via ISELECT/IREG and are local to each
CPU. When z_riscv_imsic_secondary_init() executes on CPU N, it
configures that CPU's IMSIC file.

Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>

Author: AFOliveira

arch/riscv/core/smp.c

@@ -79,6 +79,11 @@ void arch_secondary_cpu_init(int hartid)
 	/* Enable on secondary cores so that they can respond to PLIC */
 	irq_enable(RISCV_IRQ_MEXT);
 #endif /* CONFIG_PLIC_IRQ_AFFINITY */
+#if defined(CONFIG_RISCV_IMSIC) && defined(CONFIG_SMP)
+	/* Initialize IMSIC on secondary CPU */
+	extern void z_riscv_imsic_secondary_init(void);
+	z_riscv_imsic_secondary_init();
+#endif /* CONFIG_RISCV_IMSIC && CONFIG_SMP */
 #ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
 	soc_per_core_init_hook();
 #endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */

drivers/interrupt_controller/intc_riscv_imsic.c

@@ -125,18 +125,39 @@ uint32_t riscv_imsic_get_pending(const struct device *dev)
     return p0 | (p1 ? 0x80000000U : 0U); /* signal >32 pending via MSB */
 }
 
-#define IMSIC_IRQ_CONFIG_FUNC_DECLARE(inst) \
-    static void imsic_irq_config_func_##inst(void)
+/* Separate IRQ registration for hart 0 vs other harts to avoid duplicate registration */
+static void imsic_irq_config_func_0(void)
+{
+    /* Only hart 0 (instance 0) registers the global MEXT IRQ handler */
+    IRQ_CONNECT(11, 0, imsic_mext_isr, DEVICE_DT_INST_GET(0), 0);
+    irq_enable(11);
+    LOG_INF("Registered MEXT IRQ handler from hart 0 IMSIC instance");
+}
 
-#define IMSIC_IRQ_CONFIG_FUNC_DEFINE(inst) \
+#define IMSIC_IRQ_CONFIG_FUNC_DEFINE_SECONDARY(inst) \
     static void imsic_irq_config_func_##inst(void) \
     { \
-        IRQ_CONNECT(11, 0, imsic_mext_isr, DEVICE_DT_INST_GET(inst), 0); \
+        /* Secondary harts just enable MEXT locally, no IRQ_CONNECT */ \
         irq_enable(11); \
+        LOG_DBG("Hart %u IMSIC: enabled MEXT locally (no IRQ_CONNECT)", \
+                DT_INST_PROP(inst, riscv_hart_id)); \
     }
 
+/* Generate secondary IRQ config functions for instances 1+ */
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 1
+IMSIC_IRQ_CONFIG_FUNC_DEFINE_SECONDARY(1)
+#endif
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 2
+IMSIC_IRQ_CONFIG_FUNC_DEFINE_SECONDARY(2)
+#endif
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 3
+IMSIC_IRQ_CONFIG_FUNC_DEFINE_SECONDARY(3)
+#endif
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 4
+IMSIC_IRQ_CONFIG_FUNC_DEFINE_SECONDARY(4)
+#endif
+
 #define IMSIC_INIT(inst) \
-    IMSIC_IRQ_CONFIG_FUNC_DECLARE(inst); \
     static struct imsic_data imsic_data_##inst; \
     static const struct imsic_cfg imsic_cfg_##inst = { \
         .reg_base = DT_INST_REG_ADDR(inst), \
@@ -146,17 +167,30 @@ uint32_t riscv_imsic_get_pending(const struct device *dev)
     }; \
     DEVICE_DT_INST_DEFINE(inst, imsic_init, NULL, \
         &imsic_data_##inst, &imsic_cfg_##inst, \
-        PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL); \
-    IMSIC_IRQ_CONFIG_FUNC_DEFINE(inst)
+        PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
 
 DT_INST_FOREACH_STATUS_OKAY(IMSIC_INIT)
 
 /* Call IRQ config functions at POST_KERNEL level to register MEXT handler */
 static int imsic_irq_init(void)
 {
-#define IMSIC_IRQ_INIT_CALL(inst) imsic_irq_config_func_##inst();
-    DT_INST_FOREACH_STATUS_OKAY(IMSIC_IRQ_INIT_CALL)
-#undef IMSIC_IRQ_INIT_CALL
+    /* Call instance 0 (always present) */
+    imsic_irq_config_func_0();
+
+    /* Call secondary instance functions if they exist */
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 1
+    imsic_irq_config_func_1();
+#endif
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 2
+    imsic_irq_config_func_2();
+#endif
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 3
+    imsic_irq_config_func_3();
+#endif
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 4
+    imsic_irq_config_func_4();
+#endif
+
     return 0;
 }
 
@@ -208,3 +242,49 @@ void imsic_mext_isr(const void *arg)
         riscv_imsic_complete(eiid);
     }
 }
+
+#ifdef CONFIG_SMP
+/**
+ * @brief Initialize IMSIC on secondary CPUs
+ *
+ * This function is called on each secondary CPU during SMP boot to initialize
+ * the IMSIC interrupt controller on that CPU. It configures the EIDELIVERY
+ * and EITHRESHOLD CSRs to enable interrupt delivery.
+ *
+ * This follows the same pattern as smp_timer_init() for the CLINT timer.
+ *
+ * Note: IMSIC CSRs (accessed via ISELECT/IREG) are local to each CPU.
+ * When this function executes on CPU N, it configures that CPU's IMSIC file.
+ */
+void z_riscv_imsic_secondary_init(void)
+{
+    unsigned int cpu_id = arch_proc_id();
+
+    LOG_INF("IMSIC secondary init on CPU %u", cpu_id);
+
+    /* Enable interrupt delivery in MMSI mode */
+    /* EIDELIVERY[0] = 1: Enable delivery */
+    /* EIDELIVERY[30:29] = 10: MMSI mode (0x40000000) */
+    uint32_t eidelivery_value = EIDELIVERY_ENABLE | EIDELIVERY_MODE_MMSI;
+    write_imsic_csr(ICSR_EIDELIVERY, eidelivery_value);
+
+    /* Set EITHRESHOLD to 0 to allow all interrupt priorities */
+    write_imsic_csr(ICSR_EITHRESH, 0);
+
+    /* Enable MEXT interrupt on this CPU */
+    irq_enable(RISCV_IRQ_MEXT);
+
+    /* Read back to verify initialization */
+    uint32_t eidelivery_readback = read_imsic_csr(ICSR_EIDELIVERY);
+    uint32_t eithresh_readback = read_imsic_csr(ICSR_EITHRESH);
+
+    LOG_INF("CPU %u IMSIC initialized: EIDELIVERY=0x%08x EITHRESH=0x%08x",
+            cpu_id, eidelivery_readback, eithresh_readback);
+
+    /* Sanity check: verify EIDELIVERY enable bit is set */
+    if (!(eidelivery_readback & EIDELIVERY_ENABLE)) {
+        LOG_ERR("CPU %u IMSIC EIDELIVERY enable bit not set! Got 0x%08x",
+                cpu_id, eidelivery_readback);
+    }
+}
+#endif /* CONFIG_SMP */