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nzmichaelhdkalowsk
nzmichaelh
authored and
dkalowsk
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include: dt-bindings: fix and extend the ch32v00x pinctrl definitions
These were wrong and incomplete. Rebuild based on section 7.2.11 of the CH32V00XRM and added the CH32V007-only remaps. Signed-off-by: Michael Hope <michaelh@juju.nz>
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1 file changed

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-46
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‎include/zephyr/dt-bindings/pinctrl/ch32v00x-pinctrl.h‎

Lines changed: 148 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -24,17 +24,17 @@
2424
#define CH32V00X_PINMUX_USART2_RM 20
2525

2626
/* Port number with 0-3 */
27-
#define CH32V00X_PINCTRL_PORT_SHIFT 0
28-
#define CH32V00X_PINCTRL_PORT_MASK GENMASK(1, 0)
27+
#define CH32V00X_PINCTRL_PORT_SHIFT 0
28+
#define CH32V00X_PINCTRL_PORT_MASK GENMASK(1, 0)
2929
/* Pin number 0-7 */
30-
#define CH32V00X_PINCTRL_PIN_SHIFT 2
31-
#define CH32V00X_PINCTRL_PIN_MASK GENMASK(4, 2)
30+
#define CH32V00X_PINCTRL_PIN_SHIFT 2
31+
#define CH32V00X_PINCTRL_PIN_MASK GENMASK(4, 2)
3232
/* Base remap bit 0-31 */
33-
#define CH32V00X_PINCTRL_BASE_SHIFT 5
34-
#define CH32V00X_PINCTRL_BASE_MASK GENMASK(9, 5)
33+
#define CH32V00X_PINCTRL_BASE_SHIFT 5
34+
#define CH32V00X_PINCTRL_BASE_MASK GENMASK(9, 5)
3535
/* Function remapping ID 0-7 */
36-
#define CH32V00X_PINCTRL_RM_SHIFT 10
37-
#define CH32V00X_PINCTRL_RM_MASK GENMASK(12, 10)
36+
#define CH32V00X_PINCTRL_RM_SHIFT 10
37+
#define CH32V00X_PINCTRL_RM_MASK GENMASK(12, 10)
3838

3939
#define CH32V00X_PINMUX_DEFINE(port, pin, rm, remapping) \
4040
((CH32V00X_PINMUX_PORT_##port << CH32V00X_PINCTRL_PORT_SHIFT) | \
@@ -43,83 +43,179 @@
4343
(remapping << CH32V00X_PINCTRL_RM_SHIFT))
4444

4545
#define TIM1_ETR_PC5_0 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 0)
46-
#define TIM1_ETR_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 1)
47-
#define TIM1_ETR_PD4_2 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 2)
46+
#define TIM1_ETR_PD4_1 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 1)
47+
#define TIM1_ETR_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 2)
4848
#define TIM1_ETR_PC2_3 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 3)
49+
#define TIM1_ETR_PD4_4 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 4)
50+
#define TIM1_ETR_PD4_5 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 5)
51+
#define TIM1_ETR_PD4_6 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 6)
52+
#define TIM1_ETR_PB4_7 CH32V00X_PINMUX_DEFINE(PB, 4, TIM1, 7)
53+
#define TIM1_ETR_PB4_8 CH32V00X_PINMUX_DEFINE(PB, 4, TIM1, 8)
54+
#define TIM1_ETR_PB4_9 CH32V00X_PINMUX_DEFINE(PB, 4, TIM1, 9)
4955
#define TIM1_CH1_PD2_0 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 0)
50-
#define TIM1_CH1_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 1)
51-
#define TIM1_CH1_PD2_2 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 2)
56+
#define TIM1_CH1_PD2_1 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 1)
57+
#define TIM1_CH1_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 2)
5258
#define TIM1_CH1_PC4_3 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 3)
59+
#define TIM1_CH1_PA3_4 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 4)
60+
#define TIM1_CH1_PA3_5 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 5)
61+
#define TIM1_CH1_PA3_6 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 6)
62+
#define TIM1_CH1_PC4_7 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 7)
63+
#define TIM1_CH1_PC4_8 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 8)
64+
#define TIM1_CH1_PA0_9 CH32V00X_PINMUX_DEFINE(PA, 0, TIM1, 9)
5365
#define TIM1_CH2_PA1_0 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 0)
54-
#define TIM1_CH2_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 1)
55-
#define TIM1_CH2_PA1_2 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 2)
66+
#define TIM1_CH2_PA1_1 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 1)
67+
#define TIM1_CH2_PC7_2 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 2)
5668
#define TIM1_CH2_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 3)
69+
#define TIM1_CH2_PB0_4 CH32V00X_PINMUX_DEFINE(PB, 0, TIM1, 4)
70+
#define TIM1_CH2_PB0_5 CH32V00X_PINMUX_DEFINE(PB, 0, TIM1, 5)
71+
#define TIM1_CH2_PB0_6 CH32V00X_PINMUX_DEFINE(PB, 0, TIM1, 6)
72+
#define TIM1_CH2_PC5_7 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 7)
73+
#define TIM1_CH2_PC5_8 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 8)
74+
#define TIM1_CH2_PA1_9 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 9)
5775
#define TIM1_CH3_PC3_0 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 0)
58-
#define TIM1_CH3_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 1)
59-
#define TIM1_CH3_PC3_2 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 2)
76+
#define TIM1_CH3_PC3_1 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 1)
77+
#define TIM1_CH3_PC0_2 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 2)
6078
#define TIM1_CH3_PC5_3 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 3)
79+
#define TIM1_CH3_PB1_4 CH32V00X_PINMUX_DEFINE(PB, 1, TIM1, 4)
80+
#define TIM1_CH3_PC3_5 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 5)
81+
#define TIM1_CH3_PB1_6 CH32V00X_PINMUX_DEFINE(PB, 1, TIM1, 6)
82+
#define TIM1_CH3_PC6_7 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 7)
83+
#define TIM1_CH3_PC6_8 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 8)
84+
#define TIM1_CH3_PA2_9 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 9)
6185
#define TIM1_CH4_PC4_0 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 0)
62-
#define TIM1_CH4_PD3_1 CH32V00X_PINMUX_DEFINE(PD, 3, TIM1, 1)
63-
#define TIM1_CH4_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 2)
86+
#define TIM1_CH4_PC4_1 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 1)
87+
#define TIM1_CH4_PD3_2 CH32V00X_PINMUX_DEFINE(PD, 3, TIM1, 2)
6488
#define TIM1_CH4_PD4_3 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 3)
89+
#define TIM1_CH4_PD1_4 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 4)
90+
#define TIM1_CH4_PD1_5 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 5)
91+
#define TIM1_CH4_PB2_6 CH32V00X_PINMUX_DEFINE(PB, 2, TIM1, 6)
92+
#define TIM1_CH4_PC7_7 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 7)
93+
#define TIM1_CH4_PC7_8 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 8)
94+
#define TIM1_CH4_PA3_9 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 9)
6595
#define TIM1_BKIN_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 0)
66-
#define TIM1_BKIN_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 1)
67-
#define TIM1_BKIN_PC2_2 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 2)
96+
#define TIM1_BKIN_PC2_1 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 1)
97+
#define TIM1_BKIN_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 2)
6898
#define TIM1_BKIN_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 3)
99+
#define TIM1_BKIN_PB3_4 CH32V00X_PINMUX_DEFINE(PB, 3, TIM1, 4)
100+
#define TIM1_BKIN_PB3_5 CH32V00X_PINMUX_DEFINE(PB, 3, TIM1, 5)
101+
#define TIM1_BKIN_PA7_6 CH32V00X_PINMUX_DEFINE(PA, 7, TIM1, 6)
102+
#define TIM1_BKIN_PB2_7 CH32V00X_PINMUX_DEFINE(PB, 2, TIM1, 7)
103+
#define TIM1_BKIN_PB2_8 CH32V00X_PINMUX_DEFINE(PB, 2, TIM1, 8)
104+
#define TIM1_BKIN_PB2_9 CH32V00X_PINMUX_DEFINE(PB, 2, TIM1, 9)
69105
#define TIM1_CH1N_PD0_0 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 0)
70-
#define TIM1_CH1N_PC3_1 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 1)
71-
#define TIM1_CH1N_PD0_2 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 2)
106+
#define TIM1_CH1N_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 1)
107+
#define TIM1_CH1N_PC3_2 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 2)
72108
#define TIM1_CH1N_PC3_3 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 3)
109+
#define TIM1_CH1N_PA0_4 CH32V00X_PINMUX_DEFINE(PA, 0, TIM1, 4)
110+
#define TIM1_CH1N_PA0_5 CH32V00X_PINMUX_DEFINE(PA, 0, TIM1, 5)
111+
#define TIM1_CH1N_PA0_6 CH32V00X_PINMUX_DEFINE(PA, 0, TIM1, 6)
112+
#define TIM1_CH1N_PC0_7 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 7)
113+
#define TIM1_CH1N_PA3_8 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 8)
114+
#define TIM1_CH1N_PC0_9 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 9)
73115
#define TIM1_CH2N_PA2_0 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 0)
74-
#define TIM1_CH2N_PC4_1 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 1)
75-
#define TIM1_CH2N_PA2_2 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 2)
116+
#define TIM1_CH2N_PA2_1 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 1)
117+
#define TIM1_CH2N_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 2)
76118
#define TIM1_CH2N_PD2_3 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 3)
119+
#define TIM1_CH2N_PA2_4 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 4)
120+
#define TIM1_CH2N_PA2_5 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 5)
121+
#define TIM1_CH2N_PA2_6 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 6)
122+
#define TIM1_CH2N_PC1_7 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 7)
123+
#define TIM1_CH2N_PB0_8 CH32V00X_PINMUX_DEFINE(PB, 0, TIM1, 8)
124+
#define TIM1_CH2N_PC1_9 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 9)
77125
#define TIM1_CH3N_PD1_0 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 0)
78126
#define TIM1_CH3N_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 1)
79127
#define TIM1_CH3N_PD1_2 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 2)
80128
#define TIM1_CH3N_PC6_3 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 3)
129+
#define TIM1_CH3N_PD0_4 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 4)
130+
#define TIM1_CH3N_PD0_5 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 5)
131+
#define TIM1_CH3N_PD0_6 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 6)
132+
#define TIM1_CH3N_PC2_7 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 7)
133+
#define TIM1_CH3N_PB1_8 CH32V00X_PINMUX_DEFINE(PB, 1, TIM1, 8)
134+
#define TIM1_CH3N_PC2_9 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 9)
81135

82136
#define TIM2_ETR_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 0)
83-
#define TIM2_ETR_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 1)
84-
#define TIM2_ETR_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 2)
137+
#define TIM2_ETR_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 1)
138+
#define TIM2_ETR_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 2)
85139
#define TIM2_ETR_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 3)
140+
#define TIM2_ETR_PC0_4 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 4)
141+
#define TIM2_ETR_PA0_5 CH32V00X_PINMUX_DEFINE(PA, 0, TIM2, 5)
142+
#define TIM2_ETR_PB1_6 CH32V00X_PINMUX_DEFINE(PB, 1, TIM2, 6)
143+
#define TIM2_ETR_PD3_7 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 7)
86144
#define TIM2_CH1_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 0)
87-
#define TIM2_CH1_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 1)
88-
#define TIM2_CH1_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 2)
145+
#define TIM2_CH1_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 1)
146+
#define TIM2_CH1_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 2)
89147
#define TIM2_CH1_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 3)
148+
#define TIM2_CH1_PC0_4 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 4)
149+
#define TIM2_CH1_PA0_5 CH32V00X_PINMUX_DEFINE(PA, 0, TIM2, 5)
150+
#define TIM2_CH1_PB1_6 CH32V00X_PINMUX_DEFINE(PB, 1, TIM2, 6)
151+
#define TIM2_CH1_PD3_7 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 7)
90152
#define TIM2_CH2_PD3_0 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 0)
91-
#define TIM2_CH2_PC2_1 CH32V00X_PINMUX_DEFINE(PC, 2, TIM2, 1)
92-
#define TIM2_CH2_PD3_2 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 2)
153+
#define TIM2_CH2_PD3_1 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 1)
154+
#define TIM2_CH2_PC2_2 CH32V00X_PINMUX_DEFINE(PC, 2, TIM2, 2)
155+
/* CH32V007 specific remap */
156+
#define TIM2_CH2_PB3_2 CH32V00X_PINMUX_DEFINE(PB, 3, TIM2, 2)
93157
#define TIM2_CH2_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, TIM2, 3)
158+
#define TIM2_CH2_PC1_4 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 4)
159+
#define TIM2_CH2_PA1_5 CH32V00X_PINMUX_DEFINE(PA, 1, TIM2, 5)
160+
#define TIM2_CH2_PA1_6 CH32V00X_PINMUX_DEFINE(PA, 1, TIM2, 6)
161+
#define TIM2_CH2_PD4_7 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 7)
94162
#define TIM2_CH3_PC0_0 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 0)
95-
#define TIM2_CH3_PD2_1 CH32V00X_PINMUX_DEFINE(PD, 2, TIM2, 1)
96-
#define TIM2_CH3_PC0_2 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 2)
163+
#define TIM2_CH3_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 1)
164+
#define TIM2_CH3_PD2_2 CH32V00X_PINMUX_DEFINE(PD, 2, TIM2, 2)
97165
#define TIM2_CH3_PD6_3 CH32V00X_PINMUX_DEFINE(PD, 6, TIM2, 3)
166+
#define TIM2_CH3_PC3_4 CH32V00X_PINMUX_DEFINE(PC, 3, TIM2, 4)
167+
#define TIM2_CH3_PA2_5 CH32V00X_PINMUX_DEFINE(PA, 2, TIM2, 5)
168+
#define TIM2_CH3_PA2_6 CH32V00X_PINMUX_DEFINE(PA, 2, TIM2, 6)
169+
#define TIM2_CH3_PA2_7 CH32V00X_PINMUX_DEFINE(PA, 2, TIM2, 7)
98170
#define TIM2_CH4_PD7_0 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 0)
99-
#define TIM2_CH4_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 1)
100-
#define TIM2_CH4_PD7_2 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 2)
171+
#define TIM2_CH4_PD7_1 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 1)
172+
#define TIM2_CH4_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 2)
101173
#define TIM2_CH4_PD5_3 CH32V00X_PINMUX_DEFINE(PD, 5, TIM2, 3)
174+
#define TIM2_CH4_PB6_4 CH32V00X_PINMUX_DEFINE(PB, 6, TIM2, 4)
175+
#define TIM2_CH4_PA3_5 CH32V00X_PINMUX_DEFINE(PA, 3, TIM2, 5)
176+
#define TIM2_CH4_PA3_6 CH32V00X_PINMUX_DEFINE(PA, 3, TIM2, 6)
177+
#define TIM2_CH4_PA3_7 CH32V00X_PINMUX_DEFINE(PA, 3, TIM2, 7)
102178

103-
#define USART1_CK_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, USART1, 0)
104-
#define USART1_CK_PD7_1 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 1)
105-
#define USART1_CK_PD7_2 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 2)
106-
#define USART1_CK_PC5_3 CH32V00X_PINMUX_DEFINE(PC, 5, USART1, 3)
107179
#define USART1_TX_PD5_0 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 0)
108-
#define USART1_TX_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, USART1, 1)
109-
#define USART1_TX_PD6_2 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 2)
180+
#define USART1_TX_PD6_1 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 1)
181+
#define USART1_TX_PD0_2 CH32V00X_PINMUX_DEFINE(PD, 0, USART1, 2)
110182
#define USART1_TX_PC0_3 CH32V00X_PINMUX_DEFINE(PC, 0, USART1, 3)
183+
#define USART1_TX_PD1_4 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 4)
184+
#define USART1_TX_PB3_5 CH32V00X_PINMUX_DEFINE(PB, 3, USART1, 5)
185+
#define USART1_TX_PC5_6 CH32V00X_PINMUX_DEFINE(PC, 5, USART1, 6)
186+
#define USART1_TX_PB5_7 CH32V00X_PINMUX_DEFINE(PB, 5, USART1, 7)
187+
#define USART1_TX_PA0_8 CH32V00X_PINMUX_DEFINE(PA, 0, USART1, 8)
188+
#define USART1_TX_PA0_9 CH32V00X_PINMUX_DEFINE(PA, 0, USART1, 9)
111189
#define USART1_RX_PD6_0 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 0)
112-
#define USART1_RX_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 1)
113-
#define USART1_RX_PD5_2 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 2)
190+
#define USART1_RX_PD5_1 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 1)
191+
#define USART1_RX_PD1_2 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 2)
114192
#define USART1_RX_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, USART1, 3)
193+
#define USART1_RX_PB3_4 CH32V00X_PINMUX_DEFINE(PB, 3, USART1, 4)
194+
#define USART1_RX_PD1_5 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 5)
195+
#define USART1_RX_PC6_6 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 6)
196+
#define USART1_RX_PB6_7 CH32V00X_PINMUX_DEFINE(PB, 6, USART1, 7)
197+
#define USART1_RX_PA1_8 CH32V00X_PINMUX_DEFINE(PA, 1, USART1, 8)
198+
#define USART1_RX_PC4_9 CH32V00X_PINMUX_DEFINE(PC, 4, USART1, 9)
115199
#define USART1_CTS_PD3_0 CH32V00X_PINMUX_DEFINE(PD, 3, USART1, 0)
116-
#define USART1_CTS_PC3_1 CH32V00X_PINMUX_DEFINE(PC, 3, USART1, 1)
117-
#define USART1_CTS_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 2)
200+
#define USART1_CTS_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 1)
201+
#define USART1_CTS_PC3_2 CH32V00X_PINMUX_DEFINE(PC, 3, USART1, 2)
118202
#define USART1_CTS_PC6_3 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 3)
203+
#define USART1_CTS_PD7_4 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 4)
204+
#define USART1_CTS_PD7_5 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 5)
205+
#define USART1_CTS_PC7_6 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 6)
206+
#define USART1_CTS_PC7_7 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 7)
207+
#define USART1_CTS_PD2_8 CH32V00X_PINMUX_DEFINE(PD, 2, USART1, 8)
208+
#define USART1_CTS_PD5_9 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 9)
119209
#define USART1_RTS_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 0)
120-
#define USART1_RTS_PC2_1 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 1)
121-
#define USART1_RTS_PC7_2 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 2)
210+
#define USART1_RTS_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 1)
211+
#define USART1_RTS_PC2_2 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 2)
122212
#define USART1_RTS_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 3)
213+
#define USART1_RTS_PA5_4 CH32V00X_PINMUX_DEFINE(PA, 5, USART1, 4)
214+
#define USART1_RTS_PA5_5 CH32V00X_PINMUX_DEFINE(PA, 5, USART1, 5)
215+
#define USART1_RTS_PB4_6 CH32V00X_PINMUX_DEFINE(PB, 4, USART1, 6)
216+
#define USART1_RTS_PB4_7 CH32V00X_PINMUX_DEFINE(PB, 4, USART1, 7)
217+
#define USART1_RTS_PD3_8 CH32V00X_PINMUX_DEFINE(PD, 3, USART1, 8)
218+
#define USART1_RTS_PD4_9 CH32V00X_PINMUX_DEFINE(PD, 4, USART1, 9)
123219

124220
#define USART2_TX_PA7_0 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 0)
125221
#define USART2_TX_PA4_1 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 1)
@@ -182,8 +278,14 @@
182278
#define I2C1_SCL_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, I2C1, 0)
183279
#define I2C1_SCL_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, I2C1, 1)
184280
#define I2C1_SCL_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, I2C1, 2)
281+
#define I2C1_SCL_PB5_3 CH32V00X_PINMUX_DEFINE(PB, 5, I2C1, 3)
282+
#define I2C1_SCL_PB3_4 CH32V00X_PINMUX_DEFINE(PB, 3, I2C1, 4)
185283
#define I2C1_SDA_PC1_0 CH32V00X_PINMUX_DEFINE(PC, 1, I2C1, 0)
186284
#define I2C1_SDA_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, I2C1, 1)
187285
#define I2C1_SDA_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, I2C1, 2)
286+
/* CH32V007 specific remap */
287+
#define I2C1_SDA_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, I2C1, 2)
288+
#define I2C1_SDA_PB6_3 CH32V00X_PINMUX_DEFINE(PB, 6, I2C1, 3)
289+
#define I2C1_SDA_PD1_4 CH32V00X_PINMUX_DEFINE(PD, 1, I2C1, 4)
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189291
#endif /* __CH32V00X_PINCTRL_H__ */

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