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pavelvkozlovpavelvkozlov
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ARCv3:HS5x_haps: change RAM base to address 0
Since FPGA images are now built with DDR mapped to address 0 update the LINUX_RAM_BASE and LINUX_LINK_BASE in default configs for hs5x and create new haps_hs5x.dts and haps_hs5x_idu.dts. To avoid duplications created extra skeleton_haps.dtsi and skeleton_haps_idu.dtsi to use in all haps dts. Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
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8 files changed

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-133
lines changed

8 files changed

+208
-133
lines changed

‎arch/arc/boot/dts/haps_hs.dts‎

Lines changed: 1 addition & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -5,16 +5,13 @@
55
/dts-v1/;
66

77
/include/ "skeleton_hs.dtsi"
8+
/include/ "skeleton_haps.dtsi"
89

910
/ {
1011
model = "snps,zebu_hs";
1112
compatible = "snps,zebu_hs";
12-
#address-cells = <2>;
13-
#size-cells = <2>;
14-
interrupt-parent = <&core_intc>;
1513

1614
memory {
17-
device_type = "memory";
1815
/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
1916
reg = <0x0 0x80000000 0x0 0x40000000 /* 1 GB low mem */
2017
0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
@@ -23,77 +20,4 @@
2320
chosen {
2421
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
2522
};
26-
27-
aliases {
28-
serial0 = &uart0;
29-
};
30-
31-
fpga {
32-
compatible = "simple-bus";
33-
#address-cells = <1>;
34-
#size-cells = <1>;
35-
36-
/* only perip space at end of low mem accessible
37-
bus addr, parent bus addr, size */
38-
ranges = <0x80000000 0x0 0x80000000 0x80000000>;
39-
40-
core_clk: core_clk {
41-
#clock-cells = <0>;
42-
compatible = "fixed-clock";
43-
clock-frequency = <20000000>;
44-
};
45-
46-
core_intc: interrupt-controller {
47-
compatible = "snps,archs-intc";
48-
interrupt-controller;
49-
#interrupt-cells = <1>;
50-
};
51-
52-
uart0: serial@f0000000 {
53-
compatible = "ns16550a";
54-
reg = <0xf0000000 0x2000>;
55-
interrupts = <24>;
56-
clock-frequency = <20000000>;
57-
baud = <115200>;
58-
reg-shift = <2>;
59-
reg-io-width = <4>;
60-
no-loopback-test = <1>;
61-
};
62-
63-
arcpct0: pct {
64-
compatible = "snps,archs-pct";
65-
#interrupt-cells = <1>;
66-
interrupts = <20>;
67-
};
68-
69-
virtio0: virtio@f0100000 {
70-
compatible = "virtio,mmio";
71-
reg = <0xf0100000 0x2000>;
72-
interrupts = <31>;
73-
};
74-
75-
virtio1: virtio@f0102000 {
76-
compatible = "virtio,mmio";
77-
reg = <0xf0102000 0x2000>;
78-
interrupts = <32>;
79-
};
80-
81-
virtio2: virtio@f0104000 {
82-
compatible = "virtio,mmio";
83-
reg = <0xf0104000 0x2000>;
84-
interrupts = <33>;
85-
};
86-
87-
virtio3: virtio@f0106000 {
88-
compatible = "virtio,mmio";
89-
reg = <0xf0106000 0x2000>;
90-
interrupts = <34>;
91-
};
92-
93-
virtio4: virtio@f0108000 {
94-
compatible = "virtio,mmio";
95-
reg = <0xf0108000 0x2000>;
96-
interrupts = <35>;
97-
};
98-
};
9923
};

‎arch/arc/boot/dts/haps_hs5x.dts‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
/*
3+
* Copyright (C) 2023 Synopsys, Inc. (www.synopsys.com)
4+
*/
5+
/dts-v1/;
6+
7+
/include/ "skeleton_hs.dtsi"
8+
/include/ "skeleton_haps.dtsi"
9+
10+
/ {
11+
model = "snps,zebu_hs5x";
12+
compatible = "snps,zebu_hs";
13+
14+
memory {
15+
/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
16+
reg = <0x0 0x00000000 0x0 0x60000000>; /* 1.5 GB low mem */
17+
};
18+
19+
chosen {
20+
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
21+
};
22+
};

‎arch/arc/boot/dts/haps_hs5x_idu.dts‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
/*
3+
* Copyright (C) 2023 Synopsys, Inc. (www.synopsys.com)
4+
*/
5+
/dts-v1/;
6+
7+
/include/ "skeleton_hs_idu.dtsi"
8+
/include/ "skeleton_haps_idu.dtsi"
9+
10+
/ {
11+
model = "snps,zebu_hs5x-smp";
12+
compatible = "snps,zebu_hs";
13+
14+
memory {
15+
reg = <0x00000000 0x60000000>; /* 1.5 GB */
16+
};
17+
18+
chosen {
19+
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
20+
};
21+
};

‎arch/arc/boot/dts/haps_hs_idu.dts‎

Lines changed: 1 addition & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -5,70 +5,17 @@
55
/dts-v1/;
66

77
/include/ "skeleton_hs_idu.dtsi"
8+
/include/ "skeleton_haps_idu.dtsi"
89

910
/ {
1011
model = "snps,zebu_hs-smp";
1112
compatible = "snps,zebu_hs";
12-
#address-cells = <1>;
13-
#size-cells = <1>;
14-
interrupt-parent = <&core_intc>;
1513

1614
memory {
17-
device_type = "memory";
1815
reg = <0x80000000 0x40000000>; /* 1GB */
1916
};
2017

2118
chosen {
2219
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
2320
};
24-
25-
aliases {
26-
serial0 = &uart0;
27-
};
28-
29-
fpga {
30-
compatible = "simple-bus";
31-
#address-cells = <1>;
32-
#size-cells = <1>;
33-
34-
/* child and parent address space 1:1 mapped */
35-
ranges;
36-
37-
core_clk: core_clk {
38-
#clock-cells = <0>;
39-
compatible = "fixed-clock";
40-
clock-frequency = <20000000>; /* 20 MHZ */
41-
};
42-
43-
core_intc: interrupt-controller {
44-
compatible = "snps,archs-intc";
45-
interrupt-controller;
46-
#interrupt-cells = <1>;
47-
};
48-
49-
idu_intc: idu-interrupt-controller {
50-
compatible = "snps,archs-idu-intc";
51-
interrupt-controller;
52-
interrupt-parent = <&core_intc>;
53-
#interrupt-cells = <1>;
54-
};
55-
56-
uart0: serial@f0000000 {
57-
compatible = "ns16550a";
58-
reg = <0xf0000000 0x2000>;
59-
interrupt-parent = <&idu_intc>;
60-
interrupts = <0>;
61-
clock-frequency = <20000000>;
62-
baud = <115200>;
63-
reg-shift = <2>;
64-
reg-io-width = <4>;
65-
no-loopback-test = <1>;
66-
};
67-
68-
arcpct0: pct {
69-
compatible = "snps,archs-pct";
70-
#interrupt-cells = <1>;
71-
interrupts = <20>;
72-
};
73-
};
7421
};

‎arch/arc/boot/dts/skeleton_haps.dtsi‎

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,91 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
/*
3+
* Copyright (C) 2023 Synopsys, Inc. (www.synopsys.com)
4+
*/
5+
6+
/ {
7+
compatible = "snps,zebu_hs";
8+
#address-cells = <2>;
9+
#size-cells = <2>;
10+
interrupt-parent = <&core_intc>;
11+
12+
memory {
13+
device_type = "memory";
14+
/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
15+
reg = <0x0 0x80000000 0x0 0x40000000 /* 1 GB low mem */
16+
0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
17+
};
18+
19+
aliases {
20+
serial0 = &uart0;
21+
};
22+
23+
fpga {
24+
compatible = "simple-bus";
25+
#address-cells = <1>;
26+
#size-cells = <1>;
27+
28+
/* only perip space at end of low mem accessible
29+
bus addr, parent bus addr, size */
30+
ranges = <0x80000000 0x0 0x80000000 0x80000000>;
31+
32+
core_clk: core_clk {
33+
#clock-cells = <0>;
34+
compatible = "fixed-clock";
35+
clock-frequency = <20000000>;
36+
};
37+
38+
core_intc: interrupt-controller {
39+
compatible = "snps,archs-intc";
40+
interrupt-controller;
41+
#interrupt-cells = <1>;
42+
};
43+
44+
uart0: serial@f0000000 {
45+
compatible = "ns16550a";
46+
reg = <0xf0000000 0x2000>;
47+
interrupts = <24>;
48+
clock-frequency = <20000000>;
49+
baud = <115200>;
50+
reg-shift = <2>;
51+
reg-io-width = <4>;
52+
no-loopback-test = <1>;
53+
};
54+
55+
arcpct0: pct {
56+
compatible = "snps,archs-pct";
57+
#interrupt-cells = <1>;
58+
interrupts = <20>;
59+
};
60+
61+
virtio0: virtio@f0100000 {
62+
compatible = "virtio,mmio";
63+
reg = <0xf0100000 0x2000>;
64+
interrupts = <31>;
65+
};
66+
67+
virtio1: virtio@f0102000 {
68+
compatible = "virtio,mmio";
69+
reg = <0xf0102000 0x2000>;
70+
interrupts = <32>;
71+
};
72+
73+
virtio2: virtio@f0104000 {
74+
compatible = "virtio,mmio";
75+
reg = <0xf0104000 0x2000>;
76+
interrupts = <33>;
77+
};
78+
79+
virtio3: virtio@f0106000 {
80+
compatible = "virtio,mmio";
81+
reg = <0xf0106000 0x2000>;
82+
interrupts = <34>;
83+
};
84+
85+
virtio4: virtio@f0108000 {
86+
compatible = "virtio,mmio";
87+
reg = <0xf0108000 0x2000>;
88+
interrupts = <35>;
89+
};
90+
};
91+
};

‎arch/arc/boot/dts/skeleton_haps_idu.dtsi‎

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
/*
3+
* Copyright (C) 2023 Synopsys, Inc. (www.synopsys.com)
4+
*/
5+
6+
/ {
7+
compatible = "snps,zebu_hs";
8+
#address-cells = <1>;
9+
#size-cells = <1>;
10+
interrupt-parent = <&core_intc>;
11+
12+
memory {
13+
device_type = "memory";
14+
reg = <0x80000000 0x40000000>; /* 1GB */
15+
};
16+
17+
aliases {
18+
serial0 = &uart0;
19+
};
20+
21+
fpga {
22+
compatible = "simple-bus";
23+
#address-cells = <1>;
24+
#size-cells = <1>;
25+
26+
/* child and parent address space 1:1 mapped */
27+
ranges;
28+
29+
core_clk: core_clk {
30+
#clock-cells = <0>;
31+
compatible = "fixed-clock";
32+
clock-frequency = <20000000>; /* 20 MHZ */
33+
};
34+
35+
core_intc: interrupt-controller {
36+
compatible = "snps,archs-intc";
37+
interrupt-controller;
38+
#interrupt-cells = <1>;
39+
};
40+
41+
idu_intc: idu-interrupt-controller {
42+
compatible = "snps,archs-idu-intc";
43+
interrupt-controller;
44+
interrupt-parent = <&core_intc>;
45+
#interrupt-cells = <1>;
46+
};
47+
48+
uart0: serial@f0000000 {
49+
compatible = "ns16550a";
50+
reg = <0xf0000000 0x2000>;
51+
interrupt-parent = <&idu_intc>;
52+
interrupts = <0>;
53+
clock-frequency = <20000000>;
54+
baud = <115200>;
55+
reg-shift = <2>;
56+
reg-io-width = <4>;
57+
no-loopback-test = <1>;
58+
};
59+
60+
arcpct0: pct {
61+
compatible = "snps,archs-pct";
62+
#interrupt-cells = <1>;
63+
interrupts = <20>;
64+
};
65+
};
66+
};

‎arch/arc/configs/haps_hs5x_defconfig‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,9 @@ CONFIG_ISA_ARCV3=y
2020
CONFIG_ARC_CPU_HS5X=y
2121
# CONFIG_ARC_HAS_LL64 is not set
2222
# CONFIG_ARC_HAS_ACCL_REGS is not set
23-
CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs"
23+
CONFIG_LINUX_LINK_BASE=0x00000000
24+
CONFIG_LINUX_MAP_SIZE=0x60000000
25+
CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs5x"
2426
CONFIG_MODULES=y
2527
# CONFIG_BLK_DEV_BSG is not set
2628
# CONFIG_COMPACTION is not set

‎arch/arc/configs/haps_hs5x_smp_defconfig‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,9 @@ CONFIG_ISA_ARCV3=y
2121
CONFIG_ARC_CPU_HS5X=y
2222
# CONFIG_ARC_HAS_LL64 is not set
2323
# CONFIG_ARC_HAS_ACCL_REGS is not set
24-
CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs_idu"
24+
CONFIG_LINUX_LINK_BASE=0x00000000
25+
CONFIG_LINUX_MAP_SIZE=0x60000000
26+
CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs5x_idu"
2527
CONFIG_MODULES=y
2628
# CONFIG_BLK_DEV_BSG is not set
2729
# CONFIG_COMPACTION is not set

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