ARCv2: Disable SLC if IO coherency unit is absent

Without IO coherency unit for DMA to/from peripherals to work properly
it is required to flush/invalidate SLC in kernel "manually". That will
introduce performance overhead and so SLC existance won't be very
beneficial.

So we simply disable SLC if IOC is missing and then at least we have DMA
exchange without data corruption.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Author: abrodkin

arch/arc/include/asm/arcregs.h

@@ -36,6 +36,7 @@
 #define ARC_REG_ISA_CFG_BCR	0xc1
 #define ARC_REG_RTT_BCR		0xF2
 #define ARC_REG_SMART_BCR	0xFF
+#define ARC_REG_CLUSTER_BCR	0xcf
 
 /* status32 Bits Positions */
 #define STATUS_AE_BIT		5	/* Exception active */
@@ -110,6 +111,9 @@
 #define ARC_AUX_DPFP_2H         0x304
 #define ARC_AUX_DPFP_STAT       0x305
 
+/* CLUSTER Bits Positions */
+#define CLUSTER_COH_IO_SUPPORTED	24
+
 #ifndef __ASSEMBLY__
 
 /*

arch/arc/mm/cache_arc700.c

@@ -227,6 +227,16 @@ void arc_cache_init(void)
 				panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
 		}
 	}
+
+	if (is_isa_arcv2() && cpuinfo_arc700[smp_processor_id()].slc.ver) {
+		if (!(read_aux_reg(ARC_REG_CLUSTER_BCR) &
+				   (1 << CLUSTER_COH_IO_SUPPORTED))) {
+			printk("SLC\t\t: disabled, no IO coherency unit\n");
+			write_aux_reg(ARC_REG_SLC_FLUSH, 1);
+			write_aux_reg(ARC_REG_SLC_CONTROL,
+				      read_aux_reg(ARC_REG_SLC_CONTROL) | 1);
+		}
+	}
 }
 
 #define OP_INV		0x1