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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | +/* |
| 3 | + * Linux SLC(L2$) performance counter support for ARCv2 |
| 4 | + * |
| 5 | + * Copyright (C) 2014-2022 Synopsys, Inc. (www.synopsys.com) |
| 6 | + */ |
| 7 | + |
| 8 | +#ifndef __ASM_PERF_EVENT_SLC_H |
| 9 | +#define __ASM_PERF_EVENT_SLC_H |
| 10 | + |
| 11 | +#define SLC_AUX_CACHE_PCT_NUMMBER 32 // maximum number of SLC performance counters |
| 12 | +#define ARCV2_SLC_NUM_OF_EVENTS 64 // number of SLC events |
| 13 | + |
| 14 | +#define CSM_BUILD 0xE5 |
| 15 | +#define SLC_BUILD 0xCE |
| 16 | +#define SLC_AUX_CACHE_CONFIG 0x901 |
| 17 | + |
| 18 | +#define SLC_AUX_PM_CMD 0x926 |
| 19 | +#define SLC_AUX_PM_EVENT 0x927 |
| 20 | +#define SLC_AUX_PM_OVF 0x928 |
| 21 | +#define SLC_AUX_PM_CNT0 0x929 |
| 22 | +#define SLC_AUX_PM_CNT1 0x92A |
| 23 | + |
| 24 | +#define SLC_AUX_PM_CMD_ENABLE 0x0 |
| 25 | +#define SLC_AUX_PM_CMD_DISABLE 0x1 |
| 26 | +#define SLC_AUX_PM_CMD_READ 0x2 |
| 27 | +#define SLC_AUX_PM_CMD_READ_CLEAR 0x3 |
| 28 | +#define SLC_AUX_PM_CMD_PRESET 0x4 |
| 29 | +#define SLC_AUX_PM_CMD_DISABLE_ALL 0x5 |
| 30 | +#define SLC_AUX_PM_CMD_CLEAR_ALL 0x6 |
| 31 | + |
| 32 | +struct csm_build { |
| 33 | +#ifdef CONFIG_CPU_BIG_ENDIAN |
| 34 | + u32 res:8, csmecc1:2, csm_sz1:4, mpnum:2, bcycle:2, csmecc:2, csmsz:4, ver:8; |
| 35 | +#else |
| 36 | + u32 ver:8, csmsz:4, csmecc:2, bcycle:2, mpnum:2, csm_sz1:4, csmecc1:2, res:8; |
| 37 | +#endif |
| 38 | +}; |
| 39 | + |
| 40 | +struct slc_build { |
| 41 | +#ifdef CONFIG_CPU_BIG_ENDIAN |
| 42 | + u32 res:16, num:8, ver:8; |
| 43 | +#else |
| 44 | + u32 ver:8, num:8, res:16; |
| 45 | +#endif |
| 46 | +}; |
| 47 | + |
| 48 | +struct slc_aux_cache_config { |
| 49 | +#ifdef CONFIG_CPU_BIG_ENDIAN |
| 50 | + u32 r:2, b:1, pm_num:5, pms:2, tag_time:4, tbank:3, data_time:4, dbank:3, ways:2 \ |
| 51 | + lsz:2, cache_sz:4; |
| 52 | +#else |
| 53 | + u32 cache_sz:4, lsz:2, ways:2, dbank:3, data_time:4, tbank:3, tag_time:4, pms:2, \ |
| 54 | + pm_num:5, b:1, r:2; |
| 55 | +#endif |
| 56 | +}; |
| 57 | + |
| 58 | +struct slc_aux_pm_cmd { |
| 59 | +#ifdef CONFIG_CPU_BIG_ENDIAN |
| 60 | + u32 res:15, evt:8, cnum:5, cmd:4; |
| 61 | +#else |
| 62 | + u32 cmd:4, cnum:5, evt:8, res:15; |
| 63 | +#endif |
| 64 | +}; |
| 65 | + |
| 66 | +struct slc_aux_pm_event { |
| 67 | +#ifdef CONFIG_CPU_BIG_ENDIAN |
| 68 | + u32 res:23, evt:8, pe:1; |
| 69 | +#else |
| 70 | + u32 pe:1, evt:8, res:23; |
| 71 | +#endif |
| 72 | +}; |
| 73 | + |
| 74 | +struct slc_aux_pm_ovf { |
| 75 | + u32 counter_overflow; |
| 76 | +}; |
| 77 | + |
| 78 | +struct slc_aux_pm_cnt { |
| 79 | + u32 cnt; |
| 80 | +}; |
| 81 | + |
| 82 | +static void arc_perf_event_update(struct perf_event *event, |
| 83 | + struct hw_perf_event *hwc, int idx); |
| 84 | + |
| 85 | + |
| 86 | +#define ARCPMU_EVENT_NAME_LEN (31+1) // +1 for null terminator |
| 87 | + |
| 88 | +// assign names to events according to PRM |
| 89 | +char pct_names[ARCV2_SLC_NUM_OF_EVENTS][ARCPMU_EVENT_NAME_LEN]={ |
| 90 | +"TotReqPort0", |
| 91 | +"TotReqPort1", |
| 92 | +"TotReqPort2", |
| 93 | +"TotReqPort3", |
| 94 | +"TotReqPort4", |
| 95 | +"TotReqPort5", |
| 96 | +"TotReqPort6", |
| 97 | +"TotReqPort7", |
| 98 | +"TotReqPort8", |
| 99 | +"TotReqPort9", |
| 100 | +"TotReqPort10", |
| 101 | +"TotReqPort11", |
| 102 | +"TotReqPort12", |
| 103 | +"TotReqPort13", |
| 104 | +"TotReqPort14", |
| 105 | +"TotReqPort15", |
| 106 | +"TotCoreReqAllP", |
| 107 | +"TotRdReqAllPort", |
| 108 | +"TotWrReqAllPort", |
| 109 | +"TotalTagMiss", |
| 110 | +"ReadTagMiss", |
| 111 | +"WriteTagMiss", |
| 112 | +"TotStallCycDueToTagQfull", |
| 113 | +"NumOfReqWithTagQfull", |
| 114 | +"TotStallCycDueToDatQfull", |
| 115 | +"NumOfReqWithDataQfull", |
| 116 | +"TotStallCycDueToStatQfull", |
| 117 | +"NumOfReqWithStatQfull", |
| 118 | +"TotStallCycForInpReqAllP", |
| 119 | +"TotStallCycForTagMiss", |
| 120 | +"TotMissReqStall", |
| 121 | +"TotNumOf32ByteEvictions", |
| 122 | +"TotNumOfCacheLineEvictions", |
| 123 | +"TotNumOfStalledCycForInpReq", |
| 124 | +"TotNumOfStalledReq", |
| 125 | +"TotStalledWrReq", |
| 126 | +"TotStalledReq", |
| 127 | +"TotCacheMissReq", |
| 128 | +"CntCacheLineAsPendReq", |
| 129 | +"CntCacheLineAsPendTagMiss", |
| 130 | +"CntRdReqCacheLineAsTagMiss", |
| 131 | +"CntWrReqCacheLineAsTagMiss", |
| 132 | +"CntOfDataPrefetchReq", |
| 133 | +"CntOfInstrPrefetchReq", |
| 134 | +"Reserved0", |
| 135 | +"Reserved1", |
| 136 | +"Reserved2", |
| 137 | +"Reserved3", |
| 138 | +"TotStallReqForPort0", |
| 139 | +"TotStallReqForPort1", |
| 140 | +"TotStallReqForPort2", |
| 141 | +"TotStallReqForPort3", |
| 142 | +"TotStallReqForPort4", |
| 143 | +"TotStallReqForPort5", |
| 144 | +"TotStallReqForPort6", |
| 145 | +"TotStallReqForPort7", |
| 146 | +"TotStallReqForPort8", |
| 147 | +"TotStallReqForPort9", |
| 148 | +"TotStallReqForPort10", |
| 149 | +"TotStallReqForPort11", |
| 150 | +"TotStallReqForPort12", |
| 151 | +"TotStallReqForPort13", |
| 152 | +"TotStallReqForPort14", |
| 153 | +"TotStallReqForPort15" |
| 154 | +}; |
| 155 | + |
| 156 | +#define CONDITION_NONE_NUMBER 44 // using Reserved_0 condition number as no event |
| 157 | + |
| 158 | +#endif |
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