ARCv3:DBG: Add debug feature to change clock frequency

For debug purpose now we can change clock frequency using a global
variable glb_clock_freq in devtree.c
This can be useful when we have timing violations in a bitfiles and need to
reduce clock. In this case we don't need to regenerate old kernels, just
changing glb_clock_freq in MDB.

Steps to change:
1. Get clock variable address from vmlinux file
 readelf -s vmlinux | grep glb_clock_freq
 33790: 85ed7484     4 OBJECT  GLOBAL DEFAULT   16 glb_clock_freq
2. Load loader file in MDB
3. Substract 0x80000000 value from address 0x85ed7484-0x80000000 = 0x05ed7484
4. Change glb_clock_freq at address 0x05ed7484
evalq *(unsigned int *)0x05ed7484 = 20000000      (20MHz)
5. Run target

Author: xxkent

arch/arc/kernel/devtree.c

@@ -17,6 +17,8 @@
 
 static unsigned int __initdata arc_base_baud;
 
+volatile unsigned int glb_clock_freq = 50000000;
+
 unsigned int __init arc_early_base_baud(void)
 {
 	return arc_base_baud/16;
@@ -30,7 +32,7 @@ static void __init arc_set_early_base_baud(unsigned long dt_root)
 		 of_flat_dt_is_compatible(dt_root, "snps,hsdk"))
 		arc_base_baud = 33333333;	/* Fixed 33MHz clk (AXS10x & HSDK) */
 	else
-		arc_base_baud = 50000000;	/* Fixed default 50MHz */
+		arc_base_baud = glb_clock_freq;	/* Fixed default 50MHz */
 }
 #else
 #define arc_set_early_base_baud(dt_root)

drivers/clk/clk-fixed-rate.c

@@ -14,6 +14,8 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 
+extern volatile unsigned int glb_clock_freq;
+
 /*
  * DOC: basic fixed-rate clock that cannot gate
  *
@@ -148,6 +150,8 @@ static struct clk_hw *_of_fixed_clk_setup(struct device_node *node)
 	if (of_property_read_u32(node, "clock-frequency", &rate))
 		return ERR_PTR(-EIO);
 
+	rate = glb_clock_freq; // Let it be changeable in MDB during boot process.
+
 	of_property_read_u32(node, "clock-accuracy", &accuracy);
 
 	of_property_read_string(node, "clock-output-names", &clk_name);

drivers/tty/serial/8250/8250_of.c

@@ -18,6 +18,8 @@
 
 #include "8250.h"
 
+extern volatile unsigned int glb_clock_freq;
+
 struct of_serial_info {
 	struct clk *clk;
 	struct reset_control *rst;
@@ -61,6 +63,9 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
 
 		clk = clk_get_rate(info->clk);
 	}
+
+	clk = glb_clock_freq; // Let it be changeable in MDB during boot process.
+
 	/* If current-speed was set, then try not to change it. */
 	if (of_property_read_u32(np, "current-speed", &spd) == 0)
 		port->custom_divisor = clk / (16 * spd);