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ARC: [xplorer] Add support for ARC Xplorer System
The ARC Xplorer System consists of a mainboard with peripherals, on which several daughter cards can be placed. This adds support for the mainboard in combination with an ARC 770D CPU tile. Signed-off-by: Mischa Jonker <mjonker@synopsys.com>
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‎arch/arc/Kconfig‎

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@@ -79,6 +79,7 @@ menu "ARC Platform/SoC/Board"
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source "arch/arc/plat-arcfpga/Kconfig"
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source "arch/arc/plat-tb10x/Kconfig"
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source "arch/arc/plat-xplorer/Kconfig"
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#New platform adds here
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endmenu

‎arch/arc/Makefile‎

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@@ -98,6 +98,7 @@ core-y += arch/arc/boot/dts/
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core-$(CONFIG_ARC_PLAT_FPGA_LEGACY) += arch/arc/plat-arcfpga/
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core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/
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core-$(CONFIG_ARC_PLAT_XPLORER) += arch/arc/plat-xplorer/
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drivers-$(CONFIG_OPROFILE) += arch/arc/oprofile/
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‎arch/arc/plat-xplorer/Kconfig‎

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#
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# Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License version 2 as
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# published by the Free Software Foundation.
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#
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config ARC_PLAT_XPLORER
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bool "Synopsys ARC Xplorer System"
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select COMMON_CLK
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select DW_APB_ICTL
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help
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Support for the ARC Xplorer System.
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The ARC Xplorer System consists of a mainboard with peripherals,
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on which several daughter cards can be placed. The daughter cards
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typically contain a CPU and memory.
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if ARC_PLAT_XPLORER
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config XPLORER_CPUTILE_770
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select DW_APB_GPIO_INTC
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bool "ARC Xplorer CPU Tile with 770D/EM6/AS221"
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help
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This adds support for the 770D/EM6/AS221 CPU Tile. Only the ARC
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770D is supported in Linux.
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The ARC Xplorer System 770D/EM6/AS221 consists of an ARC Xplorer
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System mainboard with this daughtercard. Please use the
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xplorer_system_770.dts device tree with this configuration.
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endif

‎arch/arc/plat-xplorer/Makefile‎

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#
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# Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License version 2 as
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# published by the Free Software Foundation.
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#
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obj-$(CONFIG_XPLORER_CPUTILE_770) += xplorer770.o

‎arch/arc/plat-xplorer/xplorer770.c‎

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/*
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* ARC Xplorer System 770D/EM6/AS221 platform specific code
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*
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* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
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*
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* Mischa Jonker <mjonker@synopsys.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/clk-provider.h>
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#include <linux/of_platform.h>
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#include <asm/mach_desc.h>
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#include <asm/io.h>
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#define CPUTILE_CREG 0xf0001000
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#define FPGA_CREG 0xe0011000
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static const char *xplorer770_compat[] __initdata = {
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"snps,xplorer770",
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NULL,
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};
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#define CPUTILE_SLV_NONE 0
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#define CPUTILE_SLV_DDR_PORT0 1
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#define CPUTILE_SLV_SRAM 2
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#define CPUTILE_SLV_AXI_TUNNEL 3
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#define CPUTILE_SLV_EM6_ICCM 4
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#define CPUTILE_SLV_EM6_DCCM 5
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#define CPUTILE_SLV_AXI2APB 6
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#define CPUTILE_SLV_DDR_PORT1 7
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#define FPGA_SLV_AXI_TUNNEL_1 1
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#define FPGA_SLV_AXI_TUNNEL_2 2
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#define FPGA_SLV_SRAM 3
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#define FPGA_SLV_CONTROL 4
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static const int cputile_memmap[16][2] = {
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{CPUTILE_SLV_EM6_ICCM, 0x0}, /* 0x0000.0000 */
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{CPUTILE_SLV_SRAM, 0x0}, /* 0x1000.0000 */
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{CPUTILE_SLV_AXI_TUNNEL, 0x2}, /* 0x2000.0000 */
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{CPUTILE_SLV_AXI_TUNNEL, 0x3}, /* 0x3000.0000 */
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{CPUTILE_SLV_AXI_TUNNEL, 0x4}, /* 0x4000.0000 */
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{CPUTILE_SLV_AXI_TUNNEL, 0x5}, /* 0x5000.0000 */
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{CPUTILE_SLV_AXI_TUNNEL, 0x6}, /* 0x6000.0000 */
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{CPUTILE_SLV_AXI_TUNNEL, 0x7}, /* 0x7000.0000 */
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{CPUTILE_SLV_DDR_PORT0, 0x0}, /* 0x8000.0000 */
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{CPUTILE_SLV_DDR_PORT0, 0x1}, /* 0x9000.0000 */
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{CPUTILE_SLV_DDR_PORT0, 0x2}, /* 0xA000.0000 */
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{CPUTILE_SLV_DDR_PORT0, 0x3}, /* 0xB000.0000 */
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{CPUTILE_SLV_AXI_TUNNEL, 0xC}, /* 0xC000.0000 */
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{CPUTILE_SLV_AXI_TUNNEL, 0xD}, /* 0xD000.0000 */
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{CPUTILE_SLV_AXI_TUNNEL, 0xE}, /* 0xE000.0000 */
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{CPUTILE_SLV_AXI2APB, 0x0}, /* 0xF000.0000 */
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};
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static const int cputile_axi_tunnel_memmap[16][2] = {
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{CPUTILE_SLV_EM6_ICCM, 0x0}, /* 0x0000.0000 */
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{CPUTILE_SLV_SRAM, 0x0}, /* 0x1000.0000 */
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{CPUTILE_SLV_NONE, 0x0}, /* 0x2000.0000 */
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{CPUTILE_SLV_NONE, 0x0}, /* 0x3000.0000 */
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{CPUTILE_SLV_NONE, 0x0}, /* 0x4000.0000 */
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{CPUTILE_SLV_NONE, 0x0}, /* 0x5000.0000 */
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{CPUTILE_SLV_NONE, 0x0}, /* 0x6000.0000 */
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{CPUTILE_SLV_NONE, 0x0}, /* 0x7000.0000 */
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{CPUTILE_SLV_DDR_PORT0, 0x0}, /* 0x8000.0000 */
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{CPUTILE_SLV_DDR_PORT0, 0x1}, /* 0x9000.0000 */
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{CPUTILE_SLV_DDR_PORT0, 0x2}, /* 0xA000.0000 */
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{CPUTILE_SLV_DDR_PORT0, 0x3}, /* 0xB000.0000 */
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{CPUTILE_SLV_NONE, 0x0}, /* 0xC000.0000 */
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{CPUTILE_SLV_NONE, 0x0}, /* 0xD000.0000 */
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{CPUTILE_SLV_NONE, 0x0}, /* 0xE000.0000 */
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{CPUTILE_SLV_AXI2APB, 0x0}, /* 0xF000.0000 */
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};
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static const int fpga_memmap[16][2] = {
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{FPGA_SLV_SRAM, 0x0}, /* 0x0000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0x1}, /* 0x1000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0x2}, /* 0x2000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0x3}, /* 0x3000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0x4}, /* 0x4000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0x5}, /* 0x5000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0x6}, /* 0x6000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0x7}, /* 0x7000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0x8}, /* 0x8000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0x9}, /* 0x9000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0xA}, /* 0xA000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0xB}, /* 0xB000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0xC}, /* 0xC000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0xD}, /* 0xD000.0000 */
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{FPGA_SLV_CONTROL, 0x0}, /* 0xE000.0000 */
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{FPGA_SLV_AXI_TUNNEL_1, 0xF}, /* 0xF000.0000 */
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};
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/*
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* base + 0x00 : slave select (low 32 bits)
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* base + 0x04 : slave select (high 32 bits)
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* base + 0x08 : slave offset (low 32 bits)
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* base + 0x0C : slave offset (high 32 bits)
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*/
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static void xplorer770_set_memmap(void __iomem *base, const int memmap[16][2])
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{
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int i;
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u64 slave_select, slave_offset;
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slave_select = slave_offset = 0;
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for (i = 0; i < 16; i++) {
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slave_select |= ((u64) memmap[i][0]) << (i << 2);
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slave_offset |= ((u64) memmap[i][1]) << (i << 2);
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}
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iowrite32(slave_select & 0xffffffff, base + 0x0);
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iowrite32(slave_select >> 32, base + 0x4);
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iowrite32(slave_offset & 0xffffffff, base + 0x8);
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iowrite32(slave_offset >> 32, base + 0xC);
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}
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static void xplorer770_early_init(void)
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{
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int i;
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/* ARC 770D memory view */
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xplorer770_set_memmap((void __iomem *) CPUTILE_CREG + 0x20,
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cputile_memmap);
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iowrite32(1, (void __iomem *) CPUTILE_CREG + 0x34); /* Update */
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/* AXI tunnel memory view (incoming traffic from FPGA into CPU tile) */
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xplorer770_set_memmap((void __iomem *) CPUTILE_CREG + 0x60,
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cputile_axi_tunnel_memmap);
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iowrite32(1, (void __iomem *) CPUTILE_CREG + 0x74); /* Update */
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/* FPGA DMA peripherals memory view
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(incoming traffic from FPGA peripherals towards FPGA bus) */
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for (i = 0; i <= 10; i++)
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xplorer770_set_memmap((void __iomem *) FPGA_CREG + (i << 4),
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fpga_memmap);
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iowrite32(0x3ff, (void __iomem *) FPGA_CREG + 0x100); /* Update */
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/* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */
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iowrite32(0x01, (void __iomem *) CPUTILE_CREG + 0x120);
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/* Set up the FPGA interrupt system.*/
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/* FPGA mux interrupts to GPIO7) */
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iowrite32(0x01, (void __iomem *) FPGA_CREG + 0x214);
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/* reset ethernet and ULPI interfaces */
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iowrite32(0x18, (void __iomem *) FPGA_CREG + 0x220);
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/* map GPIO 14:10 to ARC 9:5 (IRQ mux change for rev 2 boards) */
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iowrite32(0x52, (void __iomem *) CPUTILE_CREG + 0x114);
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}
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static void xplorer770_plat_init(void)
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{
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of_clk_init(NULL);
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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MACHINE_START(XPLORER770, "xplorer770")
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.dt_compat = xplorer770_compat,
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.init_early = xplorer770_early_init,
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.init_machine = xplorer770_plat_init,
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.init_irq = NULL,
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MACHINE_END

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