arcv: add scheduling information for the Synopsys RMX-100 CPU

This commit introduces a new -mtune=rmx100 tuning option together with
relevant scheduler definitions. Instruction latencies and costs are based on
the "RMX-100 Technical Reference Manual" document (revision 0.4, 13
September 2023) and are subject to change.

The changes have been verified by running the Dhrystone and Coremark benchmarks
and observing expected (small) improvements compared to the -mtune=generic
results.

Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>

Author: artemiy-volkov

gcc/config/riscv/arcv-rmx100.md

@@ -0,0 +1,110 @@
+;; DFA scheduling description of the Synopsys RMX-100 cpu
+;; for GNU C compiler
+;; Copyright (C) 2023 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "arcv_rmx100")
+
+(define_cpu_unit "arcv_rmx100_ALU"    "arcv_rmx100")
+;(define_cpu_unit "arcv_rmx100_CSR"    "arcv_rmx100")
+(define_cpu_unit "arcv_rmx100_FPU"    "arcv_rmx100")
+(define_cpu_unit "arcv_rmx100_MPY"    "arcv_rmx100")
+(define_cpu_unit "arcv_rmx100_DIV"    "arcv_rmx100")
+(define_cpu_unit "arcv_rmx100_DMP"    "arcv_rmx100")
+
+;; Instruction reservation for arithmetic instructions.
+(define_insn_reservation "arcv_rmx100_alu_arith" 1
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "unknown, const, arith, shift, slt, multi, auipc, nop,
+			logical, move, atomic, mvpair, bitmanip, clz, ctz, cpop,
+			zicond, condmove, clmul, min, max, minu, maxu, rotate"))
+  "arcv_rmx100_ALU")
+
+(define_insn_reservation "arcv_rmx100_jmp_insn" 1
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "branch, jump, call, jalr, ret, trap"))
+  "arcv_rmx100_ALU")
+
+; DIV insn: latency may be overridden by a define_bypass
+(define_insn_reservation "arcv_rmx100_div_insn" 35
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "idiv"))
+  "arcv_rmx100_DIV*35")
+
+; MPY insn: latency may be overridden by a define_bypass
+(define_insn_reservation "arcv_rmx100_mpy32_insn" 9
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "imul"))
+  "arcv_rmx100_MPY")
+
+(define_insn_reservation "arcv_rmx100_load_insn" 3
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "load,fpload"))
+  "arcv_rmx100_DMP,nothing*2")
+
+(define_insn_reservation "arcv_rmx100_store_insn" 1
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "store,fpstore"))
+  "arcv_rmx100_DMP")
+
+(define_insn_reservation "arcv_rmx100_farith_insn" 2
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "fadd,fmul,fmadd,fcmp"))
+  "arcv_rmx100_FPU*2")
+
+(define_insn_reservation "arcv_rmx100_fdiv_insn" 17
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "fdiv,fsqrt"))
+  "arcv_rmx100_FPU*17")
+
+(define_insn_reservation "arcv_rmx100_xfer" 2
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "fmove,mtc,mfc,fcvt,fcvt_f2i,fcvt_i2f"))
+   "arcv_rmx100_FPU*2")
+
+;;(define_insn_reservation "core" 1
+;;  (eq_attr "type" "block, brk, dmb, flag, lr, sr, sync")
+;;  "arcv_rmx100_ALU0 + arcv_rmx100_ALU1 + arcv_rmx100_DMP + arcv_rmx100_MPY + arcv_rmx100_MPY64 + arcv_rmx100_DIV")
+
+(define_insn_reservation "arcv_rmx100_fmul_half" 5
+  (and (eq_attr "tune" "arcv_rmx100")
+       (and (eq_attr "type" "fadd,fmul,fmadd")
+	    (eq_attr "mode" "HF")))
+  "arcv_rmx100_FPU")
+
+(define_insn_reservation "arcv_rmx100_fmul_single" 5
+  (and (eq_attr "tune" "arcv_rmx100")
+       (and (eq_attr "type" "fadd,fmul,fmadd")
+	    (eq_attr "mode" "SF")))
+  "arcv_rmx100_FPU")
+
+(define_insn_reservation "arcv_rmx100_fmul_double" 7
+  (and (eq_attr "tune" "arcv_rmx100")
+       (and (eq_attr "type" "fadd,fmul,fmadd")
+	    (eq_attr "mode" "DF")))
+  "arcv_rmx100_FPU")
+
+(define_insn_reservation "arcv_rmx100_fdiv" 20
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "fdiv"))
+  "arcv_rmx100_FPU*20")
+
+(define_insn_reservation "arcv_rmx100_fsqrt" 25
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "fsqrt"))
+  "arcv_rmx100_FPU*25")

gcc/config/riscv/riscv-cores.def

@@ -50,6 +50,7 @@ RISCV_TUNE("xt-c920", generic, generic_ooo_tune_info)
 RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info)
 RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
 RISCV_TUNE("xiangshan-kunminghu", xiangshan, generic_ooo_tune_info)
+RISCV_TUNE("arc-v-rmx-100-series", arcv_rmx100, arcv_rmx100_tune_info)
 RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
 RISCV_TUNE("size", generic, optimize_size_tune_info)
 RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info)

gcc/config/riscv/riscv-opts.h

@@ -61,6 +61,7 @@ enum riscv_microarchitecture_type {
   generic_ooo,
   mips_p8700,
   tt_ascalon_d8,
+  arcv_rmx100,
 };
 extern enum riscv_microarchitecture_type riscv_microarchitecture;
 

gcc/config/riscv/riscv.cc

@@ -685,6 +685,30 @@ static const struct riscv_tune_param tt_ascalon_d8_tune_info = {
   true,						/* prefer-agnostic.  */
 };
 
+/* Costs to use when optimizing for Synopsys RMX-100.  */
+static const struct riscv_tune_param arcv_rmx100_tune_info = {
+  {COSTS_N_INSNS (2), COSTS_N_INSNS (2)},	/* fp_add */
+  {COSTS_N_INSNS (2), COSTS_N_INSNS (2)},	/* fp_mul */
+  {COSTS_N_INSNS (17), COSTS_N_INSNS (17)},	/* fp_div */
+  {COSTS_N_INSNS (2), COSTS_N_INSNS (2)},	/* int_mul */
+  {COSTS_N_INSNS (17), COSTS_N_INSNS (17)},	/* int_div */
+  1,						/* issue_rate */
+  4,						/* branch_cost */
+  2,						/* memory_cost */
+  4,						/* fmv_cost */
+  false,					/* slow_unaligned_access */
+  false,					/* vector_unaligned_access */
+  false,					/* use_divmod_expansion */
+  false,					/* overlap_op_by_pieces */
+  true,						/* use_zero_stride_load */
+  false,					/* speculative_sched_vsetvl */
+  RISCV_FUSE_NOTHING,				/* fusible_ops */
+  NULL,						/* vector cost */
+  NULL,						/* function_align */
+  NULL,						/* jump_align */
+  NULL,						/* loop_align */
+};
+
 /* Costs to use when optimizing for size.  */
 static const struct riscv_tune_param optimize_size_tune_info = {
   {COSTS_N_INSNS (1), COSTS_N_INSNS (1)},	/* fp_add */

gcc/config/riscv/riscv.md

@@ -672,7 +672,7 @@
 ;; Microarchitectures we know how to tune for.
 ;; Keep this in sync with enum riscv_microarchitecture.
 (define_attr "tune"
-  "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700,tt_ascalon_d8"
+  "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700,tt_ascalon_d8,arcv_rmx100"
   (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
 
 ;; Describe a user's asm statement.
@@ -4990,3 +4990,4 @@
 (include "generic-vector-ooo.md")
 (include "generic-ooo.md")
 (include "tt-ascalon-d8.md")
+(include "arcv-rmx100.md")

gcc/doc/riscv-mtune.texi

@@ -50,6 +50,8 @@ particular CPU name.  Permissible values for this option are:
 
 @samp{xiangshan-kunminghu},
 
+@samp{arc-v-rmx-100-series},
+
 @samp{generic-ooo},
 
 @samp{size},