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arcv: Add initial scheduling scheme.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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‎gcc/config/riscv/arcv-rhx100.md‎

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;; DFA scheduling description of the Synopsys RHX-100 cpu
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;; for GNU C compiler
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;; Copyright (C) 2023 Free Software Foundation, Inc.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_automaton "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_ALU_A_fuse0_early" "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_ALU_A_fuse1_early" "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_ALU_B_fuse0_early" "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_ALU_B_fuse1_early" "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_MPY32" "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_DIV" "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_DMP_fuse0" "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_DMP_fuse1" "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_fdivsqrt" "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_issueA_fuse0" "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_issueA_fuse1" "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_issueB_fuse0" "arcv_rhx100")
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(define_cpu_unit "arcv_rhx100_issueB_fuse1" "arcv_rhx100")
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;; Instruction reservation for arithmetic instructions (pipe A, pipe B).
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(define_insn_reservation "arcv_rhx100_alu_early_arith" 1
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(and (eq_attr "tune" "arcv_rhx100")
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(eq_attr "type" "unknown,move,const,arith,shift,slt,multi,auipc,nop,logical,\
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bitmanip,min,max,minu,maxu,clz,ctz,atomic,\
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condmove,mvpair,zicond,cpop,clmul"))
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"((arcv_rhx100_issueA_fuse0 + arcv_rhx100_ALU_A_fuse0_early) | (arcv_rhx100_issueA_fuse1 + arcv_rhx100_ALU_A_fuse1_early)) | ((arcv_rhx100_issueB_fuse0 + arcv_rhx100_ALU_B_fuse0_early) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_ALU_B_fuse1_early))")
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(define_insn_reservation "arcv_rhx100_jmp_insn" 1
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(and (eq_attr "tune" "arcv_rhx100")
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(eq_attr "type" "branch,jump,call,jalr,ret,trap"))
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"arcv_rhx100_issueA_fuse0 | arcv_rhx100_issueA_fuse1")
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(define_insn_reservation "arcv_rhx100_div_insn" 12
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(and (eq_attr "tune" "arcv_rhx100")
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(eq_attr "type" "idiv"))
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"arcv_rhx100_issueA_fuse0 + arcv_rhx100_DIV, nothing*11")
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(define_insn_reservation "arcv_rhx100_mpy32_insn" 4
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(and (eq_attr "tune" "arcv_rhx100")
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(eq_attr "type" "imul"))
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"arcv_rhx100_issueA_fuse0 + arcv_rhx100_MPY32, nothing*3")
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(define_insn_reservation "arcv_rhx100_load_insn" 3
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(and (eq_attr "tune" "arcv_rhx100")
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(eq_attr "type" "load,fpload"))
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"(arcv_rhx100_issueB_fuse0 + arcv_rhx100_DMP_fuse0) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_DMP_fuse1)")
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(define_insn_reservation "arcv_rhx100_store_insn" 1
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(and (eq_attr "tune" "arcv_rhx100")
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(eq_attr "type" "store,fpstore"))
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"(arcv_rhx100_issueB_fuse0 + arcv_rhx100_DMP_fuse0) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_DMP_fuse1)")
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;; (soft) floating points
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(define_insn_reservation "arcv_rhx100_xfer" 3
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(and (eq_attr "tune" "arcv_rhx100")
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(eq_attr "type" "mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fcmp"))
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"(arcv_rhx100_ALU_A_fuse0_early | arcv_rhx100_ALU_B_fuse0_early), nothing*2")
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(define_insn_reservation "arcv_rhx100_fmul" 5
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(and (eq_attr "tune" "arcv_rhx100")
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(eq_attr "type" "fadd,fmul,fmadd"))
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"(arcv_rhx100_ALU_A_fuse0_early | arcv_rhx100_ALU_B_fuse0_early)")
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(define_insn_reservation "arcv_rhx100_fdiv" 20
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(and (eq_attr "tune" "arcv_rhx100")
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(eq_attr "type" "fdiv,fsqrt"))
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"arcv_rhx100_fdivsqrt*20")
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;(final_presence_set "arcv_rhx100_issueA_fuse1" "arcv_rhx100_issueA_fuse0")
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;(final_presence_set "arcv_rhx100_issueB_fuse1" "arcv_rhx100_issueB_fuse0")
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;(final_presence_set "arcv_rhx100_ALU_A_fuse1_early" "arcv_rhx100_ALU_A_fuse0_early")
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;(final_presence_set "arcv_rhx100_ALU_B_fuse1_early" "arcv_rhx100_ALU_B_fuse0_early")
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;; Bypasses
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;(define_bypass 0 "arcv_rhx100_alu_early_arith" "arcv_rhx100_store_insn" "riscv_store_data_bypass_p")
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(define_bypass 1 "arcv_rhx100_alu_early_arith" "arcv_rhx100_store_insn" "riscv_store_data_bypass_p")
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;(define_bypass 0 "arcv_rhx100_load_insn" "arcv_rhx100_store_insn" "riscv_store_data_bypass_p")
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(define_bypass 1 "arcv_rhx100_load_insn" "arcv_rhx100_store_insn" "riscv_store_data_bypass_p")
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(define_bypass 1 "arcv_rhx100_load_insn" "arcv_rhx100_alu_early_arith")
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(define_bypass 1 "arcv_rhx100_load_insn" "arcv_rhx100_mpy*_insn")
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(define_bypass 2 "arcv_rhx100_load_insn" "arcv_rhx100_load_insn")
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(define_bypass 1 "arcv_rhx100_load_insn" "arcv_rhx100_div_insn")
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(define_bypass 3 "arcv_rhx100_mpy32_insn" "arcv_rhx100_mpy*_insn")
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(define_bypass 3 "arcv_rhx100_mpy32_insn" "arcv_rhx100_div_insn")

‎gcc/config/riscv/riscv-cores.def‎

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@@ -51,6 +51,7 @@ RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info)
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RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
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RISCV_TUNE("xiangshan-kunminghu", xiangshan, generic_ooo_tune_info)
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RISCV_TUNE("arc-v-rmx-100-series", arcv_rmx100, arcv_rmx100_tune_info)
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RISCV_TUNE("arc-v-rhx-100-series", arcv_rhx100, arcv_rhx100_tune_info)
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RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
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RISCV_TUNE("size", generic, optimize_size_tune_info)
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RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info)

‎gcc/config/riscv/riscv-opts.h‎

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@@ -62,6 +62,7 @@ enum riscv_microarchitecture_type {
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mips_p8700,
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tt_ascalon_d8,
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arcv_rmx100,
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arcv_rhx100,
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};
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extern enum riscv_microarchitecture_type riscv_microarchitecture;
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‎gcc/config/riscv/riscv.cc‎

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@@ -291,6 +291,7 @@ enum riscv_fusion_pairs
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RISCV_FUSE_BFEXT = (1 << 11),
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RISCV_FUSE_EXPANDED_LD = (1 << 12),
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RISCV_FUSE_B_ALUI = (1 << 13),
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RISCV_FUSE_ARCV = (1 << 14),
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};
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296297
/* Costs of various operations on the different architectures. */
@@ -709,6 +710,30 @@ static const struct riscv_tune_param arcv_rmx100_tune_info = {
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NULL, /* loop_align */
710711
};
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/* Costs to use when optimizing for Synopsys RHX-100. */
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static const struct riscv_tune_param arcv_rhx100_tune_info = {
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{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
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{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
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{COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
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{COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
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{COSTS_N_INSNS (27), COSTS_N_INSNS (43)}, /* int_div */
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4, /* issue_rate */
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9, /* branch_cost */
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2, /* memory_cost */
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8, /* fmv_cost */
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false, /* slow_unaligned_access */
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false, /* vector_unaligned_access */
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false, /* use_divmod_expansion */
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false, /* overlap_op_by_pieces */
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true, /* use_zero_stride_load */
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false, /* speculative_sched_vsetvl */
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RISCV_FUSE_ARCV, /* fusible_ops */
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NULL, /* vector cost */
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NULL, /* function_align */
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NULL, /* jump_align */
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NULL, /* loop_align */
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};
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/* Costs to use when optimizing for size. */
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static const struct riscv_tune_param optimize_size_tune_info = {
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{COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */
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&& REG_P (SET_DEST (set)));
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}
1038410409

10410+
/* Return TRUE if two addresses can be fused. */
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static bool
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arcv_fused_addr_p (rtx addr0, rtx addr1)
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{
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rtx base0, base1, tmp;
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HOST_WIDE_INT off0 = 0, off1 = 0;
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if (GET_CODE (addr0) == PLUS)
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{
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base0 = XEXP (addr0, 0);
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tmp = XEXP (addr0, 1);
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if (!CONST_INT_P (tmp))
10423+
return false;
10424+
off0 = INTVAL (tmp);
10425+
}
10426+
else if (REG_P (addr0))
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base0 = addr0;
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else
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return false;
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if (GET_CODE (addr1) == PLUS)
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{
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base1 = XEXP (addr1, 0);
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tmp = XEXP (addr1, 1);
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if (!CONST_INT_P (tmp))
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return false;
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off1 = INTVAL (tmp);
10438+
}
10439+
else if (REG_P (addr1))
10440+
base1 = addr1;
10441+
else
10442+
return false;
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/* Check if we have the same base. */
10445+
gcc_assert (REG_P (base0) && REG_P (base1));
10446+
if (REGNO (base0) != REGNO (base1))
10447+
return false;
10448+
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/* Offsets have to be aligned to word boundary and adjacent in memory,
10450+
but the memory operations can be narrower. */
10451+
if ((off0 % UNITS_PER_WORD == 0) && (abs (off1 - off0) == UNITS_PER_WORD))
10452+
return true;
10453+
10454+
return false;
10455+
}
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10457+
/* Return true if PREV and CURR should be kept together during scheduling. */
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10459+
static bool
10460+
arcv_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
10461+
{
10462+
rtx prev_set = single_set (prev);
10463+
rtx curr_set = single_set (curr);
10464+
/* prev and curr are simple SET insns i.e. no flag setting or branching. */
10465+
bool simple_sets_p = prev_set && curr_set && !any_condjump_p (curr);
10466+
10467+
/* Don't handle anything with a jump. */
10468+
if (!simple_sets_p)
10469+
return false;
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10471+
/* Fuse adjacent loads and stores. */
10472+
if (get_attr_type (prev) == TYPE_LOAD
10473+
&& get_attr_type (curr) == TYPE_LOAD)
10474+
{
10475+
rtx addr0 = XEXP (SET_SRC (prev_set), 0);
10476+
rtx addr1 = XEXP (SET_SRC (curr_set), 0);
10477+
10478+
if (arcv_fused_addr_p (addr0, addr1))
10479+
return true;
10480+
}
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10482+
if (get_attr_type (prev) == TYPE_STORE
10483+
&& get_attr_type (curr) == TYPE_STORE)
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{
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rtx addr0 = XEXP (SET_DEST (prev_set), 0);
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rtx addr1 = XEXP (SET_DEST (curr_set), 0);
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10488+
if (arcv_fused_addr_p (addr0, addr1))
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return true;
10490+
}
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10492+
return false;
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}
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/* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
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should be kept together during scheduling. */
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@@ -11014,6 +11124,9 @@ riscv_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
1101411124
}
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}
1101611126

11127+
if (riscv_fusion_enabled_p (RISCV_FUSE_ARCV))
11128+
return arcv_macro_fusion_pair_p (prev, curr);
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return false;
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}
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‎gcc/config/riscv/riscv.md‎

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Original file line numberDiff line numberDiff line change
@@ -672,7 +672,8 @@
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;; Microarchitectures we know how to tune for.
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;; Keep this in sync with enum riscv_microarchitecture.
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(define_attr "tune"
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"generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700,tt_ascalon_d8,arcv_rmx100"
675+
"generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700,tt_ascalon_d8,arcv_rmx100,arcv_rhx100"
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"generic,sifive_7,sifive_p400,sifive_p600,xiangshan,arcv_rhx100,generic_ooo"
676677
(const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
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678679
;; Describe a user's asm statement.
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49914992
(include "generic-ooo.md")
49924993
(include "tt-ascalon-d8.md")
49934994
(include "arcv-rmx100.md")
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(include "arcv-rhx100.md")

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