Revert "MIPS: Add conditions for use of the -mmips16e2 and -mips16 option."

This reverts commit f731fa5.

Author: wzssyqa

gcc/config/mips/mips.cc

@@ -20433,16 +20433,6 @@ mips_option_override (void)
   if (TARGET_MICROMIPS && TARGET_MIPS16)
     error ("unsupported combination: %s", "-mips16 -mmicromips");
 
-  /* Make -mmips16e2 imply -mips16 and forbid its coexistence with
-     -mmicromips as the ASE requires.  */
-  if (TARGET_MIPS16E2)
-  {
-    if (TARGET_MICROMIPS)
-      error ("unsupported combination: %s", "-mmips16e2 -mmicromips");
-
-    target_flags |= MASK_MIPS16;
-  }
-
   /* Prohibit Paired-Single and MSA combination.  This is software restriction
      rather than architectural.  */
   if (ISA_HAS_MSA && TARGET_PAIRED_SINGLE_FLOAT)
@@ -20695,15 +20685,6 @@ mips_option_override (void)
 	      "-mcompact-branches=never");
     }
 
-  /* MIPS16* ASE is forbidden in Release 6, so -mips16 is not available
-     for MIPS R6 onwards.  */
-  if ((mips_base_compression_flags & MASK_MIPS16) && mips_isa_rev >= 6)
-    error ("MIPS16* ASE is forbidden in Release 6");
-
-  /* Make sure that the user use Release[2,5] when using -mmips16e2.  */
-  if (TARGET_MIPS16E2 && mips_isa_rev < 2)
-    error ("%<-mmips16e2%> requires Release[2,5]");
-
   /* Require explicit relocs for MIPS R6 onwards.  This enables simplification
      of the compact branch and jump support through the backend.  */
   if (!TARGET_EXPLICIT_RELOCS && mips_isa_rev >= 6)

gcc/testsuite/gcc.target/mips/mips16e2-cache.c

@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips32r2 -mips16 -mmips16e2" } */
 /* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
 
 /* Test cache.  */

gcc/testsuite/gcc.target/mips/mips16e2-cmov.c

@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2 -mbranch-cost=2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2 -mbranch-cost=2" } */
 /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
 
 /* Test MOVN.  */

gcc/testsuite/gcc.target/mips/mips16e2-gp.c

@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */
 /* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */
 
 /* Generate GP-relative ADDIU.  */

gcc/testsuite/gcc.target/mips/mips16e2.c

@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */
 /* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */
 
 /* ANDI is a two operand instruction.  Hence, it won't be generated if src and