opcodes/arc: validate the {pop,push}dl_s operand

As opposed to {push,pop}l_s, the {push,pop}dl_s instructions require an
even-numbered register as their operand, since only those can be used to
designate a register pair. This commit introduces a new operand type and
uses it for these two instructions.

Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>

Author: artemiy-volkov

opcodes/arc-operands.def

@@ -39,6 +39,7 @@ ARC_OPERAND(RA_CHK, 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0)
 ARC_OPERAND(RB, 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb)
 ARC_OPERAND(RB_CHK, 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb)
 ARC_OPERAND(RBB_S, 6, 12, 0, ARC_OPERAND_IR, insert_rbb, extract_rbb)
+ARC_OPERAND(RBB_S_CHK, 6, 12, 0, ARC_OPERAND_IR, insert_rbb_chk, extract_rbb)
 ARC_OPERAND(RC, 6, 6, 0, ARC_OPERAND_IR, 0, 0)
 ARC_OPERAND(RC_CHK, 6, 6, 0, ARC_OPERAND_IR, 0, 0)
 ARC_OPERAND(RBdup, 6, 12, 0,  ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb)

opcodes/arc64-tbl.h

@@ -6570,7 +6570,7 @@
 { "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC32, POP, NONE, { BLINK_S }, { C_AA_AB }},
 
 /* popdl_s b 11000bbb1101BBB1.  */
-{ "popdl_s", 0x0000C0D1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
+{ "popdl_s", 0x0000C0D1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S_CHK }, { 0 }},
 
 /* popl_s b 11000bbb1100BBB1.  */
 { "popl_s", 0x0000C0C1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
@@ -6636,7 +6636,7 @@
 { "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC32, PUSH, NONE, { BLINK_S }, { C_AA_AW }},
 
 /* pushdl_s b 11000bbb1111BBB1.  */
-{ "pushdl_s", 0x0000C0F1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
+{ "pushdl_s", 0x0000C0F1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S_CHK }, { 0 }},
 
 /* pushl_s b 11000bbb1110BBB1.  */
 { "pushl_s", 0x0000C0E1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},

opcodes/arcxx-opc.inc

@@ -54,7 +54,7 @@ insert_rb (unsigned long long  insn,
   return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
 }
 
-/* Insert RB register into a push(d)l/pop(d)l instruction.  */
+/* Insert RB register into a pushl/popl instruction.  */
 
 static unsigned long long
 insert_rbb (unsigned long long  insn,
@@ -64,6 +64,19 @@ insert_rbb (unsigned long long  insn,
   return insn | ((value & 0x07) << 8) | (((value >> 3) & 0x07) << 1);
 }
 
+/* Insert RB register pair into a pushdl/popdl instruction.  */
+
+static unsigned long long
+insert_rbb_chk (unsigned long long  insn,
+	    long long value,
+	    const char **errmsg)
+{
+  if (value & 0x01)
+    *errmsg = _("cannot use odd number source register");
+
+  return insert_rbb(insn, value, errmsg);
+}
+
 /* Insert RB register with checks.  */
 
 static unsigned long long