arc32: Add all F16_SP_OPS

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>

Author: claziss

opcodes/arc64-tbl.h

@@ -943,6 +943,12 @@
 /* add_s 0,limm,s3 01110sss11000111.  */
 { "add_s", 0x000070C7, 0x0000F8FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, NONE, { ZA_S, LIMM_S, SIMM3_5_S }, { 0 }},
 
+/* add_s b,sp,u7 11000bbb100uuuuu.  */
+{ "add_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_ARC32, ARITH, NONE, { RB_S, SP_S, UIMM7_A32_11_S }, { 0 }},
+
+/* add_s SP,SP,u7 11000000101uuuuu.  */
+{ "add_s", 0x0000C0A0, 0x0000FFE0, ARC_OPCODE_ARC32, ARITH, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }},
+
 /* aex b,c 00100bbb00100111RBBBCCCCCCRRRRRR.  */
 { "aex", 0x20270000, 0xF8FF0000,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},
 
@@ -6557,6 +6563,12 @@
 /* or_s b,b,c 01111bbbccc00101.  */
 { "or_s", 0x00007805, 0x0000F81F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
 
+/* pop_s b 11000bbb11000001.  */
+{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC32, POP, NONE, { RB_S }, { C_AA_AB }},
+
+/* pop_s BLINK 11000RRR11010001.  */
+{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC32, POP, NONE, { BLINK_S }, { C_AA_AB }},
+
 /* popdl_s b 11000bbb1101BBB1.  */
 { "popdl_s", 0x0000C0D1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
 
@@ -6617,6 +6629,12 @@
 /* prefetchw limm,s9 00010110ssssssssS1111RR000111110.  */
 { "prefetchw", 0x1600783E, 0xFF0079FF,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
 
+/* push_s b 11000bbb11100001.  */
+{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC32, PUSH, NONE, { RB_S }, { C_AA_AW }},
+
+/* push_s blink 11000RRR11110001.  */
+{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC32, PUSH, NONE, { BLINK_S }, { C_AA_AW }},
+
 /* pushdl_s b 11000bbb1111BBB1.  */
 { "pushdl_s", 0x0000C0F1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
 
@@ -10000,6 +10018,9 @@
 /* sub_s b,b,u5 10111bbb011uuuuu.  */
 { "sub_s", 0x0000B860, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, SUB, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
 
+/* sub_s SP,SP,u7 11000001101uuuuu.  */
+{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC32, SUB, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }},
+
 /* swap<.f> b,c 00101bbb00101111FBBBCCCCCC000000.  */
 { "swap", 0x282F0000, 0xF8FF003F,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, RC }, { C_F }},