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clazissShahab Vahedi
claziss
authored and
Shahab Vahedi
committed
arc64: Update STL and STDL instructions
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-72
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2 files changed

+5
-72
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‎opcodes/arc64-opc.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -560,6 +560,11 @@
560560

561561
const struct arc_opcode arc_opcodes[] =
562562
{
563+
564+
/* STL and STDL instructions. */
565+
STL
566+
STDL
567+
563568
#include "arc64-tbl.h"
564569

565570
FP_TOP (fhmadd , FMADD , HALF)

‎opcodes/arc64-tbl.h‎

Lines changed: 0 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -9280,81 +9280,9 @@
92809280
{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARC32, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
92819281
{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARC32, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
92829282

9283-
/* stdl<.aa> c,b 00011bbb000000000BBBCCCCCC1aa111 -> stdl c , [b, s9=0] */
9284-
/* stdl<.aa> ximm,b 00011bbb000000000BBB1111001aa111 -> stdl c=60, [b, s9=0] */
9285-
/* stdl<.aa> limm,b 00011bbb000000000BBB1111101aa111 -> stdl c=62, [b, s9=0] */
9286-
/* stdl<.as> c,ximm 00011100000000000111CCCCCC1aa111 -> stdl c , [b=60, s9=0] */
9287-
/* stdl<.as> c,limm 00011110000000000111CCCCCC1aa111 -> stdl c , [b=62, s9=0] */
9288-
/* stdl<.as> ximm,ximm 000111000000000001111111001aa111 -> stdl c=60, [b=60, s9=0] */
9289-
/* stdl<.as> limm,limm 000111100000000001111111101aa111 -> stdl c=62, [b=62, s9=0] */
9290-
{ "stdl", 0x18000027, 0xF8FF8027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, RB, BRAKETdup }, { C_AA27 }},
9291-
{ "stdl", 0x18000F27, 0xF8FF8FE7, ARC_OPCODE_ARC64, STORE, NONE, { XIMM, BRAKET, RB, BRAKETdup }, { C_AA27 }},
9292-
{ "stdl", 0x18000FA7, 0xF8FF8FE7, ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, RB, BRAKETdup }, { C_AA27 }},
9293-
{ "stdl", 0x1C007027, 0xFFFFF027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, XIMM, BRAKETdup }, { C_AS27 }},
9294-
{ "stdl", 0x1E007027, 0xFFFFF027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_AS27 }},
9295-
{ "stdl", 0x1C007F27, 0xFFFFFFE7, ARC_OPCODE_ARC64, STORE, NONE, { XIMM, BRAKET, XIMMdup, BRAKETdup }, { C_AA27 }},
9296-
{ "stdl", 0x1E007FA7, 0xFFFFFFE7, ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_AA27 }},
9297-
9298-
/* stdl<.aa> c,b,s9 00011bbbssssssssSBBBCCCCCC1aa111 -> stdl c , [b, s9] */
9299-
/* stdl<.aa> ximm,b,s9 00011bbbssssssssSBBB1111001aa111 -> stdl c=60, [b, s9] */
9300-
/* stdl<.aa> limm,b,s9 00011bbbssssssssSBBB1111101aa111 -> stdl c=62, [b, s9] */
9301-
/* stdl<.as> c,ximm,s9 00011100ssssssssS111CCCCCC1aa111 -> stdl c , [b=60, s9] */
9302-
/* stdl<.as> c,limm,s9 00011110ssssssssS111CCCCCC1aa111 -> stdl c , [b=62, s9] */
9303-
/* stdl<.as> ximm,ximm,s9 00011100ssssssssS1111111001aa111 -> stdl c=60, [b=60, s9] */
9304-
/* stdl<.as> limm,limm,s9 00011110ssssssssS1111111101aa111 -> stdl c=62, [b=62, s9] */
9305-
{ "stdl", 0x18000027, 0xF8000027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }},
9306-
{ "stdl", 0x18000F27, 0xF8000FE7, ARC_OPCODE_ARC64, STORE, NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }},
9307-
{ "stdl", 0x18000FA7, 0xF8000FE7, ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }},
9308-
{ "stdl", 0x1C007027, 0xFF007027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, XIMM, SIMM9_8, BRAKETdup }, { C_AS27 }},
9309-
{ "stdl", 0x1E007027, 0xFF007027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_AS27 }},
9310-
{ "stdl", 0x1C007F27, 0xFF007FE7, ARC_OPCODE_ARC64, STORE, NONE, { XIMM, BRAKET, XIMMdup, SIMM9_8, BRAKETdup }, { C_AS27 }},
9311-
{ "stdl", 0x1E007FA7, 0xFF007FE7, ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_AS27 }},
9312-
93139283
/* sth_sZZ_H c,b,u6 10110bbbcccuuuuu. */
93149284
{ "sth_s", 0x0000B000, 0x0000F800,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }},
93159285

9316-
/* stl c,b 00011bbb000000000BBBCCCCCC0aa111 -> stl c , [b , s9=0] */
9317-
/* stl w6,b 00011bbb000000000BBBwwwwww0aa110 -> stl w6 , [b , s9=0] */
9318-
/* stl ximm,b 00011bbb000000000BBB1111000aa111 -> stl c=60, [b , s9=0] */
9319-
/* stl limm,b 00011bbb000000000BBB1111100aa111 -> stl c=62, [b , s9=0] */
9320-
/* stl c,ximm 00011100000000000111CCCCCC0RR111 -> stl c , [b=60, s9=0] */
9321-
/* stl w6,ximm 00011100000000000111wwwwww0RR110 -> stl w6 , [b=60, s9=0] */
9322-
/* stl c,limm 00011110000000000111CCCCCC0RR111 -> stl c , [b=62, s9=0] */
9323-
/* stl w6,limm 00011110000000000111wwwwww0RR110 -> stl w6 , [b=62, s9=0] */
9324-
/* stl ximm,ximm 000111000000000001111111000RR111 -> stl c=60, [b=60, s9=0] */
9325-
/* stl limm,limm 000111100000000001111111100RR111 -> stl c=62, [b=62, s9=0] */
9326-
{ "stl", 0x18000007, 0xF8FF8027, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, RB, BRAKETdup }, { C_ZZ_L }},
9327-
//{ "stl", 0x18000006, 0xF8FF8027, ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_ZZ_L }},
9328-
{ "stl", 0x18000F07, 0xF8FF8FE7, ARC_OPCODE_ARC64, STORE, NONE, { XIMM, BRAKET, RB, BRAKETdup }, { C_ZZ_L }},
9329-
{ "stl", 0x18000F87, 0xF8FF8FE7, ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, RB, BRAKETdup }, { C_ZZ_L }},
9330-
{ "stl", 0x1C007007, 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, XIMM, BRAKETdup }, { C_ZZ_L }},
9331-
{ "stl", 0x1C007006, 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_ZZ_L }},
9332-
{ "stl", 0x1E007007, 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L }},
9333-
{ "stl", 0x1E007006, 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L }},
9334-
{ "stl", 0x1C007F07, 0xFFFFFFE7, ARC_OPCODE_ARC64, STORE, NONE, { XIMM, BRAKET, XIMMdup, BRAKETdup }, { C_ZZ_L }},
9335-
{ "stl", 0x1E007F87, 0xFFFFFFE7, ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_ZZ_L }},
9336-
9337-
/* stl<.aa> c,b,s9 00011bbbssssssssSBBBCCCCCC0aa111 -> stl c , [b , s9] */
9338-
/* stl<.aa> w6,b,s9 00011bbbssssssssSBBBwwwwww0aa110 -> stl w6 , [b , s9] */
9339-
/* stl<.aa> ximm,b,s9 00011bbbssssssssSBBB1111000aa111 -> stl c=60, [b , s9] */
9340-
/* stl<.aa> limm,b,s9 00011bbbssssssssSBBB1111100aa111 -> stl c=62, [b , s9] */
9341-
/* stl<.aa> c,ximm,s9 00011100ssssssssS111CCCCCC0aa111 -> stl c , [b=60, s9] */
9342-
/* stl<.aa> w6,ximm,s9 00011100ssssssssS111wwwwww0aa110 -> stl w6 , [b=60, s9] */
9343-
/* stl<.aa> c,limm,s9 00011110ssssssssS111CCCCCC0aa111 -> stl c , [b=62, s9] */
9344-
/* stl<.aa> w6,limm,s9 00011110ssssssssS111wwwwww0aa110 -> stl w6 , [b=62, s9] */
9345-
/* stl<.aa> ximm,ximm,s9 00011100ssssssssS1111111000aa111 -> stl c=60, [b=60, s9] */
9346-
/* stl<.aa> limm,limm,s9 00011110ssssssssS1111111100aa111 -> stl c=62, [b=62, s9] */
9347-
{ "stl", 0x18000007, 0xF8000027, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 }},
9348-
//{ "stl", 0x18000006, 0xF8000027, ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 }},
9349-
{ "stl", 0x18000F07, 0xF8000FE7, ARC_OPCODE_ARC64, STORE, NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 }},
9350-
{ "stl", 0x18000F87, 0xF8000FE7, ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 }},
9351-
{ "stl", 0x1C007007, 0xFF007027, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, XIMM, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 }},
9352-
{ "stl", 0x1C007006, 0xFF007027, ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, XIMM, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 }},
9353-
{ "stl", 0x1E007007, 0xFF007027, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 }},
9354-
{ "stl", 0x1E007006, 0xFF007027, ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 }},
9355-
{ "stl", 0x1C007F07, 0xFF007FE7, ARC_OPCODE_ARC64, STORE, NONE, { XIMM, BRAKET, XIMMdup, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 }},
9356-
{ "stl", 0x1E007F87, 0xFF007FE7, ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 }},
9357-
93589286
/* st_s b,SP,u7 11000bbb010uuuuu. */
93599287
{ "st_s", 0x0000C040, 0x0000F8E0,ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
93609288

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